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Colin R Devilbiss

from Byron, MN
Age ~45
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Also known as:
Colin Robert Devilbiss
Phone and address:
834 4Th Ave NE, Byron, MN 55920
(507) 398-5134
Related to:
Philip FongDale R Peterson, 65Cara N Devilbiss, 41Carl H Peterson, 43Cara Fong, 43Tracy L Thacker, 57C L Devilbiss, 72Thomas A Devilbiss, 81Meghann J Nelson, 38Melissa D Renaud, 42Geri L Peterson, 65Kristina B Peterson, 44
Connected to:
Allison J Devilbiss, 55Kevin E Devilbiss, 64Teresa Devilches, 53Kelly J Devilder, 44Wayne H Deviley, 77Joy Devilio, 55Janette Devillasee, 74Lester M Devilla, 58Mario C Devilla, 77Sonia M Devillalta, 60

Colin Devilbiss Phones & Addresses

  • 834 4Th Ave NE, Byron, MN 55920 (507) 398-5134
  • 1212 10Th St, Rochester, MN 55901 (507) 252-8523
  • 2745 50Th St, Rochester, MN 55904 (507) 288-0314
  • 2506 18 1/2 St, Rochester, MN 55901 (507) 252-8523
  • Hancock, MI
  • Skandia, MI
  • 2745 50Th Ave SE, Rochester, MN 55904

Work

Company: Ibm Jun 2001 Position: Senior software engineer

Education

Degree: Bachelors, Bachelor of Science School / High School: Michigan Technological University 1997 to 2001 Specialities: Computer Science

Skills

Virtualization • Testing • Soa • Agile Methodologies • Unix • Perl • Software Engineering • Solution Architecture • Software Development • Shell Scripting • Linux • Debugging • Distributed Systems • C++ • Software Design • C • Operating Systems • Object Oriented Design

Industries

Information Technology And Services

Resumes

Resumes

Colin Devilbiss Photo 1

Senior Software Engineer

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Location:
834 4Th St, Byron, MN 55920
Industry:
Information Technology And Services
Work:
Ibm
Senior Software Engineer
Michigan Technological University Sep 1998 - May 2001
Computer Science Learning Center Coach
Education:
Michigan Technological University 1997 - 2001
Bachelors, Bachelor of Science, Computer Science University of Minnesota
Master of Science, Masters, Computer Science
Skills:
Virtualization
Testing
Soa
Agile Methodologies
Unix
Perl
Software Engineering
Solution Architecture
Software Development
Shell Scripting
Linux
Debugging
Distributed Systems
C++
Software Design
C
Operating Systems
Object Oriented Design

Publications

Us Patents

Restarting A Shared Virtual Resource

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US Patent:
7587723, Sep 8, 2009
Filed:
Nov 13, 2003
Appl. No.:
10/712537
Inventors:
David Charles Boutcher - Rochester MN, US
Colin Robert DeVilbiss - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 9/54
G06F 15/16
US Classification:
719325, 709201
Abstract:
An apparatus and method provide a protocol for communicating between an operating system that owns a shared resource and other operating systems that use the shared resource so that the operating systems that use the shared resource will not crash if the operating system that owns the shared resource is restarted. Messages are defined that allow handshaking between operating systems so that operating systems that share a resource will realize the resource will be unavailable for some period of time, and that allow resuming the sharing of the resource once the operating system that owns the shared resource is restarted.

Dynamically Allocating Limited System Memory For Dma Among Multiple Adapters

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US Patent:
8135934, Mar 13, 2012
Filed:
May 28, 2009
Appl. No.:
12/473573
Inventors:
Colin R. DeVilbiss - Rochester MN, US
Wayne G. Holm - Rochester MN, US
David B. Murray - Rochester MN, US
Kristopher C. Whitney - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 12/02
US Classification:
711170, 711173, 711E12001, 711E12002, 710 22
Abstract:
A method, apparatus, and computer program product dynamically allocate limited system memory for direct memory access (DMA) among a plurality of input/output (I/O) adapters in a system partition. Initially a minimum entitlement of I/O entitled memory capacity is allocated to each of the respective multiple I/O adapters. The minimum entitlement enables operation of an I/O adapter driver. Additional entitlement of I/O entitled memory capacity is selectively allocated based upon I/O demands of each I/O adapter.

Logical Memory Tags For Redirected Dma Operations

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US Patent:
20050223127, Oct 6, 2005
Filed:
Mar 31, 2004
Appl. No.:
10/815234
Inventors:
David Boutcher - Rochester MN, US
Colin DeVilbiss - Rochester MN, US
David Engebretsen - Cannon Falls MN, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY
International Classification:
G06F013/28
US Classification:
710022000, 711212000
Abstract:
A memory tag mechanism creates a logical memory tag of a first length that corresponds to an I/O address of a second length. The memory tag is “logical” because it does not represent physical memory. When an I/O adapter device driver that expects an address of the first length is invoked, the memory tag is passed. When the I/O adapter device driver makes a call to the partition manager to convert the address of the first length (i.e., memory tag) to an I/O address of the second length, the partition manager detects that the passed address is a memory tag instead of a real address, and returns the corresponding I/O address. In this manner existing device drivers that expect addresses of the first length may be used for redirected DMA, which allows performing DMA operations directly from a shared I/O adapter in a hosting partition to memory in a hosted partition.

Confirmed Delivery Of Bridged Unicast Frames

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US Patent:
20130107710, May 2, 2013
Filed:
Oct 26, 2011
Appl. No.:
13/281616
Inventors:
Colin R. DeVilbiss - Rochester MN, US
Scott T. Robinson - Rochester MN, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
H04L 12/56
H04L 12/26
US Classification:
370235
Abstract:
Systems and methods to reduce table lookups and network traffic are provided. A bridging device may receive a unicast frame to be bridged. The unicast frame may be transmitted to at least one network of a plurality of networks. The bridging device may determine if the unicast frame was successfully delivered to the at least one network.

Identifying Slow Nodes In A Computing Environment

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US Patent:
20230089565, Mar 23, 2023
Filed:
Sep 22, 2021
Appl. No.:
17/481966
Inventors:
- Armonk NY, US
Colin R. Devilbiss - Byron MN, US
Timothy J. Schimke - Stewartville MN, US
International Classification:
G06F 9/50
Abstract:
A first operation in a computing environment with a set of nodes is monitored. A subset of nodes that are utilized by the first operation is identified. The subset of nodes is a subset of the set of nodes. For each node in the subset of nodes, an operation counter for the respective node is incremented and an operation time for the first operation is added to a total operation timer for the respective node. For each node in the subset of nodes, the respective total operation timer is divided by the respective operation counter. A node in the subset of nodes that appears to be slow is identified based on the dividing. The data for multiple operations could be aggregated in the operation counters and total operation timers for each node within the set of nodes, enabling nodes that appear to be slow to be identified on aggregate data.
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Colin R Devilbiss from Byron, MN, age ~45 Get Report