Resumes
Resumes
Claude Ceccon Phones & Addresses
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Corona, NM
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Phoenix, AZ
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1255 River Rd, Tucson, AZ 85704
Business Records
Name / Title
Company / Classification
Phones & Addresses
Owner
Ip&L
Business Services at Non-Commercial Site
Business Services at Non-Commercial Site
1255 W Riv Rd, Tucson, AZ 85704
Publications
Us Patents
Electronic System For Measuring Time, Impact Energy And Other Athletic Parameters
View pageUS Patent:
41999878, Apr 29, 1980
Filed:
Nov 30, 1978
Appl. No.:
5/965103
Inventors:
William R. Bauers - Santa Ana CA
Paul Mioduski - Tucson AZ
Claude R. Ceccon - Tucson AZ
Paul Mioduski - Tucson AZ
Claude R. Ceccon - Tucson AZ
International Classification:
B01L 502
US Classification:
73379
Abstract:
An electronic system for selectively measuring predetermined athletic parameters, such as reaction time and impact energy, and for displaying the results of the measurements is disclosed. The system includes transducer apparatus for sensing a participant's athletic reaction or motion, a selectively actuable timing circuitry responsive to initiation for providing after a pseudo-random delay a start signal to which the participant is to respond, and logic circuitry responsive to the transducer output. The timing circuit utilizes information provided by the logic circuitry and provides outputs indicative of predetermined parameters of the participant's motion or reaction time. The disclosed system further includes display apparatus responsive to the timing circuit outputs for displaying indicia of the measured parameters.
Object Building Method For Self Configuring Computer Network
View pageUS Patent:
46226338, Nov 11, 1986
Filed:
Dec 6, 1983
Appl. No.:
6/558783
Inventors:
Claude R. Ceccon - Tucson AZ
Joseph N. Kovara - Tucson AZ
Joseph N. Kovara - Tucson AZ
Assignee:
Tri Sigma Corporation - Scottsdale AZ
International Classification:
G06F 1516
G06F 1340
G06F 900
G06F 1340
G06F 900
US Classification:
364200
Abstract:
A computer system including a first processor and a plurality of removable interface circuits is operated by storing hardware descriptors for each interface circuit, each hardware descriptor including a name and an attribute of each component of the interface. Software templates describing each data structure and pointers to code to be executed to build software objects corresponding to each component contained on any interface board in the system are stored, which code is executed to building such software objects. The hardware descriptors are utilized to obtain lists of components of each interface from a data base, using names of such components to obtain software templates corresponding to the named component and pointing to software that utilizes the software template to build the software object representing a function that can be performed by the component, assigns a name to that software object and entering the name and corresponding software object into the data base.
Self Configuring Computer Network With Automatic Bus Exchange Of Module Identification Numbers And Processor Assigned Module Numbers
View pageUS Patent:
46601414, Apr 21, 1987
Filed:
Dec 6, 1983
Appl. No.:
6/558779
Inventors:
Claude R. Ceccon - Tucson AZ
Joseph N. Kovara - Tucson AZ
Paul C. Mioduski - Tucson AZ
Joseph N. Kovara - Tucson AZ
Paul C. Mioduski - Tucson AZ
Assignee:
Tri Sigma Corporation - Scottsdale AZ
International Classification:
G06F 1516
G06F 1300
G06F 1342
G06F 1300
G06F 1342
US Classification:
364200
Abstract:
In a computer network having a system bus, a system processor connected to the system bus, and a plurality of local processors each connected to a respective local bus each having a plurality of interface cards attached thereto, each interface card includes an identification ROM. Each interface card responds to an initial reset signal enabling that interface card to respond to the same initial address. Each local processor outputs that initial address. The closest interface card of each local bus responds by transmitting information from its identification ROM to the requesting local processor, which then assigns an address to the closest interface card, which then automatically sets circuitry that enables the next closest interface card to respond to the initial address. The procedure is repeated to assign unique addresses to all of the interface cards.
Self Configuring Bus Structure For Computer Network
View pageUS Patent:
46351922, Jan 6, 1987
Filed:
Dec 6, 1983
Appl. No.:
6/558778
Inventors:
Claude R. Ceccon - Tucson AZ
Paul C. Mioduski - Tucson AZ
Paul C. Mioduski - Tucson AZ
Assignee:
Tri Sigma Corporation - Scottsdale AZ
International Classification:
G06F 1300
G06F 1340
G06F 1340
US Classification:
364200
Abstract:
A computer bus structure includes a plurality of separate bus segments on a mother board. Plugging in of each of a plurality of interface boards automatically connects the right-hand portion of a particular bus segment to the left-hand portion of an adjacent bus segment so that a local bus of the needed length is created from the separate bus segments by the plugging of a processor board and a plurality of interface boards into successive adjacent connector slots, respectively, of the mother board. Insertion of processor boards into a particular connection slot of the mother board prevents the two bus segments adjacent thereto from being connected.