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Chulmin Jung

from San Diego, CA
Age ~57
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Also known as:
Chul Min Jung, Chul M Jung
Related to:
Sheri D Lim, 59Chulwoo JungM Gene Lim, 89Euijin Lim, 80Susanna Lim, 52Alexander J Lim, 56Yongjai G Lim
Connected to:
Alferd E Jung, 90Andy B Jung, 48Annabelle B Jung, 68Ashley K Jung, 42Bo H JungBoon S Jung, 72Chelsea Jung, 37Chuck S Jung, 98Edgar J Jung, 49Eunae A Jung, 46

Chulmin Jung Phones & Addresses

  • San Diego, CA
  • Eden Prairie, MN
  • 1508 Riverstone Ln, Boise, ID 83706 (208) 345-8287
  • 5701 Center St, Pittsburgh, PA 15206 (412) 363-6208
  • 1725 Bear Run Dr, Pittsburgh, PA 15237 (412) 847-0370

Resumes

Resumes

Chulmin Jung Photo 1

Chulmin Jung

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Position:
Sr staff/Mgr at Qualcomm
Location:
Greater San Diego Area
Industry:
Electrical/Electronic Manufacturing
Work:
Qualcomm - Greater San Diego Area since Jun 2012
Sr staff/Mgr
Broadcom Jul 2009 - May 2012
Principal Designer
Seagate Technology Mar 2008 - Jul 2009
Principal designer
Micron Technology Oct 2002 - Feb 2008
Designer
Samsung Semiconductor Feb 1991 - Jul 2000
Senior designer
Education:
Carnegie Mellon University 2001 - 2002
Seoul National University 1989 - 1991
Seoul National University 1985 - 1989
Skills:
PLL
CMOS
Semiconductors
Analog Circuit Design

Publications

Us Patents

Data Path Having Grounded Precharge Operation And Test Compression Capability

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US Patent:
7061817, Jun 13, 2006
Filed:
Jun 30, 2004
Appl. No.:
10/883619
Inventors:
George Raad - Boise ID, US
Chulmin Jung - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 29/00
US Classification:
365201, 365203, 365190
Abstract:
A data path for coupling data between a memory cell and an input/output (IO) line sense amplifier. An IO line coupling circuit is coupled to a pair of global data lines and a pair of local data lines to couple and decouple each of the global data lines to and from a voltage supply based on the voltage levels of the local data lines for the memory read operation. For the memory write operation, the IO line coupling circuit couples and decouples each of the global data lines to and from a respective one of the local data lines. The data path also includes a first precharge circuit coupled to the global data lines to couple the global data lines to ground to precharge the signal lines prior to a memory read or write operation, and can further include a test compression circuit coupled to the global data lines.

Data Path Having Grounded Precharge Operation And Test Compression Capability

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US Patent:
7170806, Jan 30, 2007
Filed:
Mar 3, 2006
Appl. No.:
11/367467
Inventors:
George Raad - Boise ID, US
Chulmin Jung - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 7/00
US Classification:
365205, 365201, 365203
Abstract:
A data path for coupling data between a memory cell and an input/output (IO) line sense amplifier. An IO line coupling circuit is coupled to a pair of global data lines and a pair of local data lines to couple and decouple each of the global data lines to and from a voltage supply based on the voltage levels of the local data lines for the memory read operation. For the memory write operation, the IO line coupling circuit couples and decouples each of the global data lines to and from a respective one of the local data lines. The data path also includes a first precharge circuit coupled to the global data lines to couple the global data lines to ground to precharge the signal lines prior to a memory read or write operation, and can further include a test compression circuit coupled to the global data lines.

Line Amplifier To Supplement Line Driver In An Integrated Circuit

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US Patent:
7212460, May 1, 2007
Filed:
Dec 5, 2005
Appl. No.:
11/294729
Inventors:
Chulmin Jung - Boise ID, US
George Raad - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 7/00
G11C 8/00
US Classification:
365207, 365208, 36518905
Abstract:
A method and circuitry for boosting a driven signal along a circuit line so as to reduce RC delays is disclosed. In one embodiment, the circuitry includes a line amplifier positioned at a distance from the circuitry that drives signals onto the line, for example, across a memory array. The line amplifier detects the driven signal on the line at early stages, and even before the signal reaches its full potential, the amplifier amplifies that signal and drives it back to the line to help boost the detected signal. In a preferred embodiment, the amplifier comprises a differential amplifier capable of boosting one of two input signal lines. In an alternative embodiment, the amplifier output may additionally input to a feedback loop, which loop ultimately drives a pull-up transistor to boost the detected signal and passes it back to the line to even further assist the differential amplifier in boosting. Use of the disclosed circuitry benefits, as one example, the boosting of a DRAM column select line that passes a long distance through the memory array.

Apparatus With Equalizing Voltage Generation Circuit And Methods Of Use

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US Patent:
7433249, Oct 7, 2008
Filed:
Feb 6, 2006
Appl. No.:
11/347961
Inventors:
Chulmin Jung - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 5/14
US Classification:
36518909, 36518907, 365226, 327536, 327538, 323281
Abstract:
A memory device includes an equalization voltage generator. The equalization voltage generator includes an oscillator and a charge pump to produce a first voltage, which may be used as an equalization voltage for pairs of complementary digit lines. The oscillator is controlled by an oscillator control signal, which is produced by a feedback and control loop of the equalization voltage generator. The feedback and control loop includes a reference generator circuit to produce a stable, internal reference signal that is clamped at a maximum reference voltage. A comparator of the feedback and control loop compares the internal reference signal with a second voltage, which is proportional to the first voltage. The comparator causes the oscillator to turn on when the second voltage is lower than the reference voltage, and causes the oscillator to turn off when the second voltage is higher than the reference voltage.

Power Saving Sensing Scheme For Solid State Memory

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US Patent:
7567465, Jul 28, 2009
Filed:
Aug 30, 2007
Appl. No.:
11/847559
Inventors:
Chulmin Jung - Boise ID, US
Kang Yong Kim - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 7/00
US Classification:
36518905, 36518902, 365206, 365207
Abstract:
Methods and apparatus are disclosed, such as those involving a solid state memory device. One such method includes selecting a plurality of memory cells in a memory array. States of a plurality of data bits stored in the selected plurality of memory cells are determined. In determining the states of the plurality of data bits, a portion of the plurality of data bits are sensed faster than others. The plurality of data bits are sequentially provided as an output. In one embodiment, the portion of the plurality of data bits includes the first bit of the sequential output of the memory device.

Input-Output Line Sense Amplifier Having Adjustable Output Drive Capability

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US Patent:
7596039, Sep 29, 2009
Filed:
Feb 14, 2007
Appl. No.:
11/706937
Inventors:
Kang Yong Kim - Boise ID, US
Chulmin Jung - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 7/00
G11C 7/02
US Classification:
36518915, 36518917, 365207
Abstract:
An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line sense amplifier having an output driver stage having a plurality of different programmable output drive capacities to tailor the output drive of the sense amplifier.

Array Sense Amplifiers, Memory Devices And Systems Including Same, And Methods Of Operation

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US Patent:
7606097, Oct 20, 2009
Filed:
Dec 27, 2006
Appl. No.:
11/646735
Inventors:
Chulmin Jung - Boise ID, US
Tae Kim - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 7/02
US Classification:
365207, 365205, 365196, 365204, 365203
Abstract:
A sense amplifier having an amplifier stage with decreased gain is described. The sense amplifier includes a first input/output (“I/O”) node and a second complementary I/O node. The sense amplifier includes two amplifier stages, each for amplifying a signal on one of the I/O nodes. The first amplifier stage, having a first conductivity-type, amplifies one of the I/O node towards a first voltage. The second amplifier stage, having a second conductivity-type, amplifies the other I/O node towards a second voltage. The sense amplifier also includes a resistance circuit coupled to the second amplifier stage to reduce the gain of the second amplifier stage thereby reducing the rate of amplification of the signal on the corresponding I/O node.

Signal Transfer Apparatus And Methods

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US Patent:
7701782, Apr 20, 2010
Filed:
Sep 13, 2007
Appl. No.:
11/854933
Inventors:
Chulmin Jung - Boise ID, US
Kang Yong Kim - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 11/34
US Classification:
36518905, 365220, 365221
Abstract:
Some embodiments include a number of nodes configured to receive a number of signals. The signals may represent information stored in a number of memory cells of a device such as a memory device. The device may include a number of transfer paths having storage elements coupled between the nodes and an output node. The transfer paths may be configured to transfer a selected signal of the signals from one of the nodes to the output node via one of the transfer paths. The transfer paths may be configured to hold a value of the selected signal in only one of the storage elements. Each of the transfer paths may include only one of the storage elements. Other embodiments including additional apparatus, systems, and methods are disclosed.
Control profile
Chulmin Jung from San Diego, CA, age ~57 Get Report