Choh Fei Yeap

20140036578, Feb 6, 2014

Jan 15, 2013

13/741869

Younghwi Yang - Seoul, KR
Bin Yang - San Diego CA, US
Choh Fei Yeap - San Diego CA, US

QUALCOMM Incorporated - San Diego CA

G11C 11/412

365154

Methods and apparatuses for static memory cells. A static memory cell may include a first pass gate transistor including a first back gate node and a second pass gate transistor including a second back gate node. The static memory cell may include a first pull down transistor including a third back gate node and a second pull down transistor including a fourth back gate node. The source node of the first pull down transistor, source node of the second pull down transistor, and first, second, third, and fourth back gate nodes are electrically coupled to each other to form a common node.

20140070364, Mar 13, 2014

Sep 13, 2012

13/613008

Yong Park - San Diego CA, US
Zhongze Wang - San Diego CA, US
John J. Zhu - San Diego CA, US
Choh Fei Yeap - San Diego CA, US

QUALCOMM Incorporated - San Diego CA

H01L 23/525

257530, 438600

An electrically programmable gate oxide anti-fuse device includes an anti-fuse aperture having anti-fuse links that include metallic and/or semiconductor electrodes with a dielectric layer in between. The dielectric layer may be an interlayer dielectric (ILD), an intermetal dielectric (IMD) or an etch stop layer. The anti-fuse device may includes a semiconductor substrate having a conductive gate (e.g., a high K metal gate) disposed on a surface of the substrate, and a dielectric layer disposed on the conductive gate. A stacked contact can be disposed on the dielectric layer and a gate contact is disposed on an exposed portion of the gate.

20120212245, Aug 23, 2012

Feb 1, 2012

13/364091

Angelo Pinto - San Diego CA, US
Martin L. Villafana - Bonita CA, US
You-Wen Yau - San Diego CA, US
Homyar C. Mogul - San Diego CA, US
Lavakumar Ranganathan - San Diego CA, US
Rohan V. Gupte - San Diego CA, US
Weijia Qi - San Diego CA, US
Kent J. Pingrey - San Diego CA, US
Carlos P. Aguilar - San Diego CA, US
Paul J. Giotta - Redington Beach FL, US
Leon Y. Leung - San Diego CA, US
Jina M. Antosz - Escondido CA, US
Bhupen M. Shah - Carlsbad CA, US
Choh fei Yeap - San Diego CA, US
Michael J. Campbell - Encinitas CA, US
Lawrence A. Elugbadebo - San Diego CA, US
Allen A.B. Hogan - San Diego CA, US

QUALCOMM Incorporated - San Diego CA

G01R 31/3187
H01L 23/58

3247503, 257 48, 257E23002

An integrated circuit is disclosed. The integrated circuit includes an insulating material layer. The integrated circuit also includes a metal structure. Furthermore, the integrated circuit includes a via through the insulating material layer that is coupled to the metal structure for testing insulating material by applying dynamic voltage switching to two adjacent metal components of the metal structure.

20200161189, May 21, 2020

Jan 24, 2020

16/752157

- San Diego CA, US
Jeffrey XU - San Diego CA, US
Da YANG - San Diego CA, US
Kern RIM - San Diego CA, US
Choh fei YEAP - San Diego CA, US

H01L 21/8238
H01L 29/10
H01L 27/092
H01L 21/3065
H01L 29/66

A method of producing a FinFET device with fin pitch of less than 20 nm is presented. In accordance with some embodiments, fins are deposited on sidewall spacers, which themselves are deposited on mandrels. The mandrels can be formed by lithographic processes while the fins and sidewall spacers formed by deposition technologies.

20180082906, Mar 22, 2018

Sep 20, 2016

15/271043

- San Diego CA, US
Jeffrey XU - San Diego CA, US
Da YANG - San Diego CA, US
Kern RIM - San Diego CA, US
Choh fei YEAP - San Diego CA, US

H01L 21/8238
H01L 27/092
H01L 29/10
H01L 21/3065

A method of producing a FinFET device with fin pitch of less than 20 nm is presented. In accordance with some embodiments, fins are deposited on sidewall spacers, which themselves are deposited on mandrels. The mandrels can be formed by lithographic processes while the fins and sidewall spacers formed by deposition technologies.

20170278842, Sep 28, 2017

Mar 25, 2016

15/081702

- San Diego CA, US
Jeffrey Junhao Xu - San Diego CA, US
Kern Rim - San Diego CA, US
Choh Fei Yeap - San Diego CA, US

H01L 27/06
H01L 29/66
H01L 29/161
H01L 21/8234
H01L 29/78
H01L 29/06

An integrated circuit includes a FinFET and a nanostructure FET. The integrated circuit includes a bulk substrate. The integrated circuit also includes a fin field effect transistor (FinFET) coupled to the bulk substrate. The FinFET includes a first source region, a first drain region, and a fin extending between the first source region and the first drain region. The integrated circuit also includes a nanostructure FET coupled to the bulk substrate. The nanostructure FET includes a second source region, a second drain region, and a stack of at least two nanostructures extending between the second source region and the second drain region.

20170271202, Sep 21, 2017

Aug 5, 2016

15/229535

- San Diego CA, US
John Jianhong Zhu - San Diego CA, US
Choh Fei Yeap - San Diego CA, US

H01L 21/768
H01L 23/498

Forming self-aligned vertical interconnect accesses (vias) in interconnect structures for integrated circuits (ICs) is disclosed. To reduce or avoid misalignment of a via to an underlying, interconnected metal line, vias are fabricated in the interconnect structure to be self-aligned with an underlying, interconnected metal line. In this regard, underlying metal lines are formed in a dielectric layer. A recess is formed in an underlying metal line below a top surface of an inter-layer dielectric. A stop layer is disposed above the inter-layer dielectric and within the recess of the underlying metal line. The stop layer allows a via tunnel to be formed (e.g., etched) down within the recess of the underlying metal line to self-align the via tunnel with the underlying metal line. A conductive material is then deposited in the via tunnel extending into the recess to form the self-aligned via interconnected to the underlying metal line.

20170221884, Aug 3, 2017

Apr 12, 2016

15/097142

- San Diego CA, US
Stanley Seungchul Song - San Diego CA, US
Mustafa Badaroglu - Kessel-Lo, BE
John Jianhong Zhu - San Diego CA, US
Junjing Bao - San Diego CA, US
Jeffrey Junhao Xu - San Diego CA, US
Da Yang - San Diego CA, US
Matthew Michael Nowak - San Diego CA, US
Choh Fei Yeap - San Diego CA, US

H01L 27/088
H01L 29/06
H01L 21/8234
H01L 27/02

A device includes a substrate, a first nanowire field effect transistor (FET), and a second nanowire FET positioned between the substrate and the first nanowire FET. The device also includes a first nanowire electrically coupled to the first nanowire FET and to the second nanowire FET.