Chester M Nibby from 183 Bridge St, Beverly Farms, MA 01915, age 81

Resumes

Dv Engineer At Nortel

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Location:

Greater Boston Area

Industry:

Telecommunications

Experience:

Nortel (Public Company; NT; Telecommunications industry): DV Engineer, (2006-Present) I have designed a number of constrained random, self checking verification environments using mostly SystemVerilog and some SystemC.Sycamore Networks (Public Company; Telecommunicati...

Publications

Us Patents

Dynamic Memory System Which Includes Apparatus For Performing Refresh Operations In Parallel With Normal Memory Operations

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US Patent:

41853237, Jan 22, 1980

Filed:

Jul 20, 1978

Appl. No.:

5/926480

Inventors:

Robert B. Johnson - Billerica MA
Chester M. Nibby - Peabody MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G11C 1300

US Classification:

365222

Abstract:

A memory subsystem for processing memory requests includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes arrays of memory elements corresponding to a number of storage locations, separate addressing and data output circuits. The system further includes common timing, refresh and control circuits. When the memory request specifies a predetermined type of memory operation, the control circuits generate signals for refreshing a location within the memory unit from which data is not being fetched. The control circuits, upon the completion of the refresh operation, in response to another predetermined memory request, refreshes the corresponding row within the other unit in parallel with fetching data from first unit. Upon completing refresh operations within both units, the control circuits generate a control signal for inhibiting the refresh circuits from performing a mandatory refresh operation, upon a row of memory elements within the memory units in which access to the memory system is inhibited temporarily, enabling memory operations to continue without interruption.

Method Of Constructing A Number Of Different Memory Systems

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US Patent:

42558522, Mar 17, 1981

Filed:

Jul 16, 1979

Appl. No.:

6/057783

Inventors:

Robert B. Johnson - Billerica MA
Chester M. Nibby - Peabody MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

H05K 332

US Classification:

29837

Abstract:

A printed circuit board assembly includes at least two layers which is able to accommodate a subsystem such as a memory subsystem designed to have one or more optional features. The two layers of the printed circuit board when etched include the required number of horizontal and vertical paths to be connected to all of the integrated circuit chips to be positioned and interconnected thereon. The required holes for such integrated circuit chips when drilled include first sets of holes for mounting groups of integrated circuit chips required for implementing a first group of features and which are to be interconnected to the other integrated circuit chips of the subsystem mounted on the different sections of the board. Second sets of holes are included on the board so as to have a predetermined relationship with the first sets of holes for mounting alternative groups of integrated circuit chips to be interconnected in a manner to implement other features. Thereafter, the circuit board is populated with only those integrated circuit chips required for construction of a memory subsystem with one or more selected features.

Identification Apparatus For Use In A Controller To Facilitate The Diagnosis Of Faults

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US Patent:

44687311, Aug 28, 1984

Filed:

Dec 15, 1981

Appl. No.:

6/330971

Inventors:

Robert B. Johnson - Billerica MA
Chester M. Nibby - Peabody MA
Edward R. Salas - Billerica MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 1110

US Classification:

364200

Abstract:

A data processing system includes a main memory system which couples in common with a central processing unit to a bus for transfer of data between the central processing unit and memory system. The memory system includes a plurality of memory controllers, each of which controls the operation of a number of memory modules. Each controller also includes reconfiguration apparatus for enabling reconfiguration of the memory system upon detection of a fault. The reconfiguration apparatus includes apparatus for identifying the type and design revision of the controller associated therewith enabling more expeditious fault diagnosis based upon status signals provided by the controller during diagnostic testing by the central processing unit.

Memory Identification Apparatus And Method

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US Patent:

45450102, Oct 1, 1985

Filed:

Mar 31, 1983

Appl. No.:

6/480964

Inventors:

Edward R. Salas - Billerica MA
Edwin P. Fisher - N. Abington MA
Robert B. Johnson - Billerica MA
Chester M. Nibby - Peabody MA
Daniel A. Boudreau - Billerica MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 1300

US Classification:

364200

Abstract:

A memory system includes at least one or more memory module boards identical in construction and a single computer board containing the control circuits for controlling memory operations. Each board plugs into the main board and includes a memory section having a number of rows of memory chips and an identification section containing circuits for generating signals indicating the board density and the type of memory parts used in constructing the board's memory section. The main board control circuits include a number of decoder circuits which couple to the identification and to the memory section of each memory module board. The decoder circuits receive different address bit combinations of a predetermined multibit address portion of each memory request address. In response to signals generated by the identification sections of the installed memory boards, the decoder circuits are selectively enabled to decode those bit combinations of the address portion specified by the sections for enabling successive addressing of all of the blocks of location within the system.

Means For Transferring Firmware Signals Between A Control Store And A Microprocessor Means Through A Reduced Number Of Connections By Transfer According To Firmware Signal Function

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US Patent:

49166018, Apr 10, 1990

Filed:

Dec 19, 1988

Appl. No.:

7/286581

Inventors:

Richard P. Kelly - Nashua NH
Robert V. Ledoux - Litchfield NH
Chester M. Nibby - Beverly MA

Assignee:

Bull HN Information Systems Inc. - Billerica MA

International Classification:

G06F 922

US Classification:

364200

Abstract:

A firmware controlled microprocessor plugged into a printed circuit board received firmware signals from a control store mounted on the printed circuit board. The number of pins required for transferring firmware signals is reduced by time sharing pins with firmware signal required for the full cycle of operation and firmware signal required only during the second half of the cycle of operation.

Sequential Chip Select Decode Apparatus And Method

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US Patent:

43239650, Apr 6, 1982

Filed:

Jan 8, 1980

Appl. No.:

6/110523

Inventors:

Robert B. Johnson - Billerica MA
Chester M. Nibby - Peabody MA
Dana Moore - Dover MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 1300

US Classification:

364200

Abstract:

A memory subsystem which couples to a multiword bus for processing memory requests received therefrom includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem receives as part of each memory request an address, the least significant portion of which selects the row of chips to be accessed within one of the pair of memory units. Address decode circuits include gating circuits which couple to both module units. The gating circuits are interconnected so that the decoding of the least significant address bits results in the generation of a pair of row address strobe signals. These signals enable simultaneously the rows of RAM chips for access within both module units for read out of information to a multiword bus eliminating any delay in address incrementing.

Memory Controller With Burst Mode Capability

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US Patent:

43665390, Dec 28, 1982

Filed:

Oct 31, 1980

Appl. No.:

6/202819

Inventors:

Robert B. Johnson - Billerica MA
Chester M. Nibby - Peabody MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 1300

US Classification:

364200

Abstract:

A memory controller coupled to a number of memory module units and includes a number of control circuits. The control circuits include address counter circuits which are loaded with a portion of the address of each predetermined type of command or memory request from a requesting device. This command when decoded causes the controller to read out from the memory module units a predetermined number of word pairs starting with the location specified by the stored address portion.

Apparatus For Loading And Verifying A Control Store Memory Of A Central Subsystem

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US Patent:

49106660, Mar 20, 1990

Filed:

Dec 18, 1986

Appl. No.:

6/943984

Inventors:

Chester M. Nibby - Beverly MA
Richard C. Zelley - North Chelmsford MA
Kenneth E. Bruce - Milford NH
George J. Barlow - Tewksbury MA
James W. Keeley - Nashua NH

Assignee:

Bull HN Information Systems Inc. - Billerica MA

International Classification:

G06F 1300

US Classification:

364200

Abstract:

A central subsystem of a data processing system includes a writable control store which is loaded with firmware to control the central subsystem operations. The central subsystem logic is responsive to a sequence of commands from a system management facility to load the control store and verify that the control store firmware is loaded correctly.

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