Chenwei J Yin

55901344, Dec 31, 1996

Jun 7, 1995

8/477213

Chenwei J. Yin - Richardson TX

Texas Instruments Incorporated - Dallas TX

G11C 2900

371 215

An integrated circuit includes read/write memory and non-memory circuitry. A detector generates a count of the number of bits of each data words recalled from the memory having a predetermined logic state. An adder accumulates the count for plural data words over a period of time into a count register. The integrated circuit may be tested by lading each data word of the read/write memory with a first logic state and repeatedly addressing said read/write memory circuitry with a predetermined number of each possible address in sequence. The resulting count in the count register is compared with an expected count. The integrated circuit may also be tested by loading a predetermined addressable storage location with another logic state while loading all other addressable storage locations with the first logic state and repeatedly addressing the predetermined addressable storage location. The resulting count in the count register is compared with another expected count. The non-memory circuitry is preferably digital to analog converters, whose outputs may be compared to test their operation.

55965830, Jan 21, 1997

Jul 19, 1991

7/734344

William R. Krenik - Garland TX
Louis J. Izzi - Plano TX
Chenwei J. Yin - Richardson TX

Texas Instruments Incorporated - Dallas TX

G01R 3128

371 221

Test circuitry (90) is provided which includes a multiplexer (118) for selectively receiving multiple bit control words defining test functions to be executed by said test circuitry and for outputting data from said test circuitry. A plurality of digital data inputs (96) are provided for receiving multiple bit words of digital data and a plurality of analog data inputs (98) are provided for receiving analog data. A register (120) is coupled to multiplexer (118) for storing a one of the multiple bit words received by multiplexer (118). Control circuitry (122) is coupled to register (120) for controlling execution of the test function defined by the control word being held in register (120). First test circuitry (112) is coupled to digital data inputs (96) and control circuitry (122) for passing digital data words received at digital data inputs (96) to multiplexer (118) for output in response to a first control word of said control words being held in register (120).

53715179, Dec 6, 1994

Nov 8, 1991

7/791757

Louis Izzi - Plano TX
William R. Krenik - Garland TX
Henry T. Yung - Richardson TX
Chenwei J. Yin - Richardson TX
Carrell R. Killebrew - Sugar Land TX
Karl Guttag - Missouri City TX
Jerry R. Van Aken - Sugar Land TX
Jeffrey Nye - Houston TX
Richard Simpson - Bedford, GB2
Mike Asal - Sugar Land TX

Texas Instruments Incorporated - Dallas TX

G09G 128

345199

A color palette selects a master clock from plural clock signals received at clock input terminals in response to a master clock selection control word received at control data terminals. A circuit forms a plurality of divided down clock signals from selected divide ratios of the master clock. A circuit selects a shift clock from among the divided down clock signals in response to at least some bits of an output clock selection control word received at the control data terminals. A circuit selectively enables and disables the shift clock in response to blanking data. A circuit selects a video clock from among the divided down clock signals in response to at least some bits of the output clock selection control word. A circuit synchronizes multiple bit words of color code received at color code input terminals with the master clock. A circuit outputs at least one memory recall address in response to receiving each multiple bit word of color code.

57176973, Feb 10, 1998

Aug 24, 1992

7/934598

Chenwei J. Yin - Richardson TX

Texas Instruments Incorporated - Dallas TX

G06F 1110

371 215

An integrated circuit including a semiconductor chip and chip circuitry including memory circuitry and additional non-memory circuitry all fabricated on the semiconductor chip. The chip circuitry has a defined set of locations having logic states including a first logic state and at least one other logic state. A semiconductor chip package has pins connected to the chip circuitry. Accumulator circuitry on-chip and connected to the chip circuitry generates a count of the number of locations in the set that have the first logic state. The semiconductor chip package has pins connected to the chip circuitry and accumulator circuitry for external access to the count. Other integrated circuits, palette devices, computer graphics systems and methods are disclosed.

53132319, May 17, 1994

Mar 24, 1992

7/856431

Chenwei J. Yin - Richardson TX
Richard C. Nail - Plano TX
Louis J. Izzi - Plano TX
Edison H. Chiu - Richardson TX

Texas Instruments Incorporated - Dallas TX

G09G 128

345199

A color palette is provided having a plurality input terminals for receiving a plurality of bits of data having an order. A two color path is included which comprises first circuitry coupled to the input terminals for selectively reversing the order of the plurality of bits of data. Second circuitry is coupled to the first circuitry and is operable in a first mode to pass all of the plurality of bits of data received from the first circuitry and in a second mode has at least one word comprising selected ones of the plurality of bits, the selected ones of the bits having a bit order. The third circuitry is provided coupled to the second circuitry and operable to pass all of the bits of data received from the second circuitry in the first mode and operable to selectively reverse the ordering of the selected ones of the bits and pass be at least one word received from the second circuitry in the second mode. The fourth circuitry is further provided coupled to the third circuitry inoperable to receive bits of data passed from the circuitry and select for output as at least one word of true color data at least some of the bits.

54464820, Aug 29, 1995

Nov 13, 1991

7/792503

Jerry R. Van Aken - Sugar Land TX
Chenwei J. Yin - Richardson TX

Texas Instruments Incorporated - Dallas TX

G09G 128

345199

A circuit 83, 97 is provided for selectively interpreting data received in a format selected from the big-endian and little-endian formats to an other one of the big-endian and little-endian formats and includes an array of j sequentially ordered data input terminals for receiving a j-bit word of data formatted in a preselected one of the big-endian and little-endian formats. An array of j sequentially ordered first AND gates 126 is provided, each first AND gate 126 having first and second input ports and an output port, the first input port of the n. sup. th first AND gate 126 coupled to the n. sup. th one of the input terminals, the second input ports of the first AND gates 126 coupled to a control signal. An array of j sequentially ordered second AND gates 128 are provided, and each second AND gate 128 having first and second input ports and an output port, of the first input port of an n. sup. th one of the second AND gates 128 coupled to a (j-n+1). sup.

54000572, Mar 21, 1995

Sep 3, 1993

8/116476

Chenwei J. Yin - Richardson TX

Texas Instruments Incorporated - Dallas TX

G09G 506

345199

An integrated circuit including a semiconductor chip and chip circuitry including memory circuitry and additional non-memory circuitry all fabricated on the semiconductor chip. The chip circuitry has a defined set of locations having logic states including a first logic state and at least one other logic state. A semiconductor chip package has pins connected to the chip circuitry. Accumulator circuitry on-chip and connected to the chip circuitry generates a count of the the number of locations in the set that have the first logic state. The semiconductor chip package has pins connected to the chip circuitry and accumulator circuitry for external access to the count. Other integrated circuits, palette devices, computer graphics systems and methods are disclosed.