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Chayan Kumar Seal

from Beaverton, OR
Age ~52

Chayan Seal Phones & Addresses

  • 640 NW Pacific Grove Dr, Beaverton, OR 97006 (503) 617-0880
  • 16922 Watermark Ln, Beaverton, OR 97006 (503) 617-0880
  • 1337 189Th Ave, Beaverton, OR 97006 (503) 617-0880
  • 16325 Schendel Ave, Beaverton, OR 97006 (503) 617-0880
  • 3120 John Olsen Ave, Hillsboro, OR 97124 (503) 617-7575
  • 12028 Bryony Dr, Austin, TX 78739 (512) 330-4859
  • 401 39Th St, Austin, TX 78751 (512) 452-9951

Resumes

Resumes

Chayan Seal Photo 1

Principal Engineer

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Location:
Portland, OR
Industry:
Semiconductors
Work:
Intel Corporation
Principal Engineer
Education:
Seth Anandram Jaipuria School
St. Joseph's College
Skills:
Vlsi
Static Timing Analysis
Asic
Semiconductors
Soc
Physical Design
Microprocessors
Circuit Design
Processors
Cmos
Low Power Design
Logic Design
Intel
Timing Closure
Signal Integrity
Rtl Design
Application Specific Integrated Circuits
Lvs
System on A Chip
Very Large Scale Integration
Languages:
Bengali
English
Hindi
Sanskrit
Chayan Seal Photo 2

Chayan Seal

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Location:
Portland, Oregon Area
Industry:
Semiconductors
Skills:
Static Timing Analysis
Microprocessors
SoC
Physical Design
ASIC
VLSI
Timing Closure
Low-power Design
Processors
Circuit Design
Logic Design
Intel
Signal Integrity
Semiconductors
LVS
Languages:
Bengali
English
Hindi

Publications

Us Patents

Method, Apparatus And System Of Domino Multiplexing

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US Patent:
20060001450, Jan 5, 2006
Filed:
Jun 30, 2004
Appl. No.:
10/879260
Inventors:
Chayan Seal - Beaverton OR, US
Marijan Persun - Beaverton OR, US
International Classification:
H03K 19/00
US Classification:
326093000
Abstract:
Embodiments of the present invention provide a method, apparatus and system for domino multiplexing including sustaining a first domino block output in a preconditioning state using a second domino block output.

Fully Interruptible Domino Latch

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US Patent:
20090167358, Jul 2, 2009
Filed:
Dec 28, 2007
Appl. No.:
11/966241
Inventors:
Chayan Kumar SEAL - Austin TX, US
International Classification:
H03K 19/096
US Classification:
326 98
Abstract:
A domino latch is provided that comprises a forward path circuit and a feedback path circuit. The feedback path includes a plurality of keeper transistors, an inverter, and at least one interrupt transistor to cut off the feedback path circuit and prevent signal contention on the output node between the feedback path circuit and the forward path circuit.
Chayan Kumar Seal from Beaverton, OR, age ~52 Get Report