Charles Ed Chang

6452433, Sep 17, 2002

May 31, 2000

09/583441

Charles Chang - Newbury Park CA
Steven Beccue - Oxnard CA

Conexant Systems, Inc. - Newport Beach CA

H03K 3289

327202, 327201

An improved flip-flop circuit exhibits a higher phase margin than conventional flip-flop circuits without a substantial increase in operating power. The flip-flop circuit includes a master latch circuit operatively coupled to a slave latch circuit. The flip-flop circuit uses any number of techniques to delay the hold-to-sample transition of the slave latch circuit relative to the sample-to-hold transition of the master latch circuit. The delay enables the flip-flop circuit to better tolerate clock/data timing alignment issues. In a first embodiment, the slave clock signal is delayed relative to the master clock signal. In a second embodiment, the master clock signal buffer is unbalanced such that its duty cycle is skewed to produce unequal sample and hold periods. In a third embodiment, the master latch circuit is unbalanced to create an unequal delay associated with the sampling and holding periods.

6526109, Feb 25, 2003

Dec 5, 2000

09/615627

Charles Chang - Thousand Oaks CA
Bo Zhang - Las Flores CA
Zhihao Lao - Thousand Oaks CA

Conexant Systems, Inc. - Newport Beach CA

H04L 2500

375371, 375376, 375374, 327158

Modern fiber optic networks typically transfer data using encoding in which the clock is transmitted along with the data, for example in NRZ format. In order to use the clock to process the data, the clock signal must be extracted from the data signal. Because the data and clock may travel through different circuit paths they may have different propagation delays and a phase offset between the clock and data may result. Data and clock phase offsets are more problematical as data transmission speed increases. Furthermore the data/phase offset is typically not constant and may change with a variety of variables. To compensate for the changing offset, one or more variable delays are inserted in the phase detector circuitry. The timing of the variable delay is controlled by a bang-bang phase detector, such as an Alexander phase detector, which determines if the clock is leading, lagging, or in phase with the data. The delay control loops are low bandwidth, because the phase offset generally changes slowly, and because the loops should not respond to temporary upsets such as noise spikes.

6563145, May 13, 2003

Dec 29, 1999

09/474624

Charles E. Chang - Newbury Park CA, 91320
Richard L. Pierson - Thousand Oaks CA, 91360
Peter J. Zampardi - Westlake Village CA, 91361
Peter M. Asbeck - San Diego CA, 92130

H01L 29739

257197, 257200, 438 35, 438235, 438342, 438796

A compound collector double heterojunction bipolar transistor (CCHBT) incorporates a collector comprising two layers: a wide bandgap collector region (e. g. , GaAs), and a narrow bandgap collector region (e. g. , InGaP). The higher electric field is supported in the wide bandgap region, thereby increasing breakdown voltage and reducing offset voltage. At the same time, the use of wide bandgap material in the depleted portion of the collector, and a higher mobility material toward the end and outside of the depletion region, reduces series resistance as well as knee voltage.

6628605, Sep 30, 2003

Jul 21, 1999

09/358198

Charles E. Chang - Newbury Park CA

Conexant Systems, Inc. - Newport Beach CA

H04J 1100

370208, 370343, 375356

A switch suitable for use in high-bandwidth environments is disclosed. The switch eliminates the need for inter-stage jitter compensation by determining the timing signals associated with each data input and then re-timing the data based upon the timing signals at the switch output. Bandwidth is conserved by routing timing signals through a multiplexer that preferably determines the difference between the timing signal and a reference signal, combines the difference signal with other difference signals calculated for other data inputs, and then transmits the multiplexed difference signals to a demultiplexer. Suitable multiplexing schemes include time division multiplexing, wavelength division multiplexing, code division multiple access (CDMA) multiplexing, as well as various combinations of suitable multiplexing methods.

6636077, Oct 21, 2003

Jun 11, 1999

09/330875

Charles E. Chang - Thousand Oaks CA
Andre Metzger - La Jolla CA

Conexant Systems, Inc. - Newport Beach CA

H03K 19082

326105, 327407

A high-isolation, low-power high-speed multiplexer circuit suitably includes a buffer stage and a current steering tree stage. By employing common select lines for both stages of the circuit, both the input buffer and the deselected channel provide cumulative isolation for the deselected channels.

7127391, Oct 24, 2006

Nov 20, 2003

10/720000

Charles E. Chang - Thousand Oaks CA, US
Daniel Scott Draper - Portland OR, US

Mindspeed Technologies, Inc. - Newport Beach CA

G10L 21/00

704230, 375316

A method and apparatus is disclosed for reducing the error rate in a received signal by determining and establishing an optimal slice point for a decision device, or optimal operational parameters. In one embodiment, a processor monitors a received signal to determine signal characteristics, such as a peak signal level or phase value. A table look-up operation may occur in a data table or other processing may occur and, based on the signal characteristics, an optimal slice point may be determined. In one embodiment the look-up operation may also reveal one or more optimal operational parameters that, if adopted, will further reduce the error rate. A receiving station may communicate these optimal operational parameters to a transmitting station to modify operation of the transmitting station. Also disclosed is a method and apparatus for self-testing a communication system and channel to determine optimal slice points and operational parameters.

7813381, Oct 12, 2010

May 7, 2004

10/841762

Charles E. Chang - Coto de Caza CA, US
Wim F. Cops - Newport Beach CA, US
Brian Hostetter - Mission Viejo CA, US

Mindspeed Technologies, Inc. - Newport Beach CA

H04J 3/06

370503

Various systems and methods for automatic data rate detection are provided. In one embodiment, a system is provided that includes a clock and data recovery circuit embodied in a first integrated circuit, the clock and data recovery circuit being configured to re-clock a data stream. The system also includes an automatic rate detection system embodied in a second integrated circuit, where the first integrated circuit is in data communication with the second integrated circuit. Also, the automatic rate detection system is configured to determine a data rate of the data stream upon identifying a transition in the data rate of the data stream based upon the state of the at least one status flag received from the clock and data recovery circuit.

8358489, Jan 22, 2013

Aug 27, 2010

12/807082

Charles Chang - Coto De Caza CA, US

International Rectifier Corporation - El Segundo CA

H02J 7/00

361 18, 307150

According to one embodiment, a smart photovoltaic (PV) panel comprises a plurality of PV cell groups each including at least one PV cell. The smart PV panel also includes at least one serial boost combiner circuit (SBCC) configured to receive an output from the plurality of PV cell groups as inputs. Each SBCC comprises several boost blocks connected in parallel, each of the boost blocks including a switching device and a respective boost block output directly connected to an output node of the SBCC. In addition a corresponding power terminal of each of the switching devices is directly connected to a common ground node of the SBCC. In one embodiment, the smart PV panel also includes a power inverter coupled to the one or more SBCCs and a communication unit interfaced with a local controller.