Carlos H Obregon

52763625, Jan 4, 1994

May 6, 1992

7/879646

Carlos D. Obregon - Phoenix AZ
Daniel T. Bizuneh - Tempe AZ
Vikrant Chaudhry - Tempe AZ
Michael A. Wells - Chandler AZ

Motorola, Inc. - Schaumburg IL

H03K 1908
H03K 190175
H03K 1901

307446

The present invention includes a circuit having an input section that is operated from an operating voltage which is lower than a supply voltage of the circuit. The operating voltage is established so that the operating voltage minus the voltage of a high level TTL signal is less than an upper level threshold voltage of the input section. The circuit couples the output of the input section to the supply voltage thereby increasing the voltage on the output of the input section to a voltage greater than the operating voltage. In addition, the circuit enables a current source during a portion of a low-to-high transition on an output of the circuit. The current source provides high current drive during the portion of the transition. Since the current source is only enabled during the portion of the transition, static power dissipation is minimized.

50557149, Oct 8, 1991

Oct 29, 1990

7/605203

Carlos D. Obregon - Tempe AZ

Motorola, Inc. - Schaumburg IL

H03K 1716
H03K 512

307443

A circuit for reducing negative ground bounce on the ground reference of a CMOS circuit having an input terminal and an output terminal includes an output buffer having an input coupled to the input terminal of the circuit and an output coupled to the output terminal of the circuit. A NOR gate has first and second inputs respectively which are coupled to the input and output terminals of the circuit. An injector circuit is coupled to an output of the NOR gate and to the input terminal of the circuit for providing a predetermined current to the output terminal of the circuit.

52870219, Feb 15, 1994

May 6, 1992

7/880109

Carlos D. Obregon - Phoenix AZ
Eric D. Neely - Mesa AZ
Michael A. Wells - Chandler AZ

Motorola, Inc. - Schaumburg IL

H03K 1760
H03K 1902
H03K 1920
H03K 1716

307570

A plurality of transistors (22, 23, 27) are utilized to provide a low noise high-to-low transition (40) on an output (19) of a circuit (10). The transistors (22, 23, 27) are sequentially enabled to vary a rate of change of output current thereby minimizing noise created by the high-to-low transition (40). A first transistor (22) is enabled to provide a low rate of change. Subsequently, a second transistor (23) is enabled to provide a higher rate of change. Then, just prior to disabling the second transistor (23) a third transistor (27) is enabled to provide a d. c. level.

54324629, Jul 11, 1995

Apr 30, 1993

8/054495

Carlos D. Obregon - Phoenix AZ
Michael A. Wells - Chandler AZ
Eric D. Neely - Mesa AZ

Motorola, Inc. - Schaumburg IL

H03K 1908
H03K 190175

326 21

The present invention includes an input buffer circuit (10) having sleep mode and bus hold capability. An input section (11) of the buffer circuit is operated from an operating voltage which is lower than a supply voltage of the buffer circuit thereby minimizing the static power dissipation. Sleep mode circuitry (15, 36, 38) is included for effectively disconnecting an input signal from the rest of the buffer circuit thereby minimizing dynamic power dissipation. Bus hold circuitry (40) is included for holding the logic state appearing at an output of the input buffer circuit when the input signal is removed thereby further reducing the static power dissipation.

55460216, Aug 13, 1996

Feb 14, 1994

8/194974

Daniel T. Bizuneh - Tempe AZ
Carlos Obregon - Phoenix AZ
Michael A. Wells - Chandler AZ
Eric D. Neely - Mesa AZ

Motorola, Inc. - Schaumburg IL

H03K 190175

326 86

A 3 state BiCMOS output buffer (100) with power down capability has been provided. The buffer includes an input stage (102), responsive to an input signal, an output coupled to both a pull-up driver (114), and an output pull-down driver (116) wherein the drivers provide an output signal at an output of the buffer in response to the input signal. Additionally, the buffer includes a power down sense circuit (108), coupled to a power supply node (118), for turning off an output pull-up transistor (214) when the power supply node is powered down and thus eliminating leakage paths within the buffer. The buffer also includes a noise limiting circuit (112) for slowing down a high to low transition at the output of the buffer thereby reducing the switching noise of the buffer while not affecting the overall speed of the buffer.

50086359, Apr 16, 1991

Jun 25, 1990

7/542542

Carl C. Hanke - Mesa AZ
Carlos D. Obregon - Tempe AZ
Ahmad H. Atriss - Chandler AZ

Motorola, Inc. - Schaumburg IL

H03L 706

331 1A

A PLL lock indicator circuit for indicating when a phase-lock-loop circuit is in lock includes a gate circuit coupled to the phase/frequency detector of the phase-lock-loop circuit for providing an output logic signal that is responsive to output logic signals from the phase/frequency detector being in a predetermined state. A counter circuit is enabled by the output logic signal of the gate circuit for providing an output logic signal when the counter circuit has reached a predetermined count. A latch circuit is responsive to the output logic signal of the counter circuit for providing a lock signal at an output terminal of the circuit, the lock signal being indicative of when the PLL circuit is in phase lock.

49704087, Nov 13, 1990

Oct 30, 1989

7/428678

Carl C. Hanke - Mesa AZ
Carlos D. Obregon - Tempe AZ
Timothy W. Sutton - Mesa AZ

Motorola, Inc. - Schaumburg

H03K 1720
H03K 1722
H03K 17284
H03K 17687

3072723

The output signal of a CMOS power-on reset circuit changes state upon detecting a predetermined threshold of the power supply voltage during the start-up transient. During the power-up of the power supply voltage, the output signal of the power-on reset circuit ramps up with the power supply voltage until the latter reaches a first predetermined level whereat a control signal begins to track the increasing power supply voltage, less two diodes potentials. Upon reaching the turn-on potential of a transistor, the control signal activates an inverter to substantially reduce the output signal signifying that the power supply voltage level is sufficient for the operation of external circuitry. The output signal then disables the current flowing through the power-on reset circuit to save power consumption.