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Carlos Gamero Phones & Addresses

  • Lutz, FL
  • 3210 Escondido Dr, Orlando, FL 32827 (352) 369-9771
  • 3644 Laurel Bluff Cir, High Point, NC 27265
  • Irvine, CA
  • Laguna Hills, CA
  • Huntington Beach, CA
  • Sunrise, FL
  • Coconut Creek, FL
  • Gainesville, FL

Resumes

Resumes

Carlos Gamero Photo 1

Circuit Design Contractor

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Location:
17611 Shadyside Cir, Lutz, FL 33549
Industry:
Semiconductors
Work:

Circuit Design Contractor
Skills:
Vhdl
Interests:
Learning Chinese
Programming
Certifications:
Introduction To Computer Science and Programming Using Python (83%)
Introduction To Computational Thinking and Data Analysis (92%)
Principles of Computing (97%)
Introduction To Computing With Java (90%)
The Analytics Edge (89%)
Data Analysis and Statistical Inference (92%)
Computing For Data Analysis (100%)
Data Analysis (86%)
Machine Learning (83%)
Introduction To Recommender Systems (76%)
Algorithms: Design and Analysis - Part 1 (86%)
Coding the Matrix: Linear Algebra Through Computer Science (98%)
Stat2.1X Introduction To Statistics: Descriptive Statistics (96%)
Stat2.2X Introduction To Statistics: Probability (71%)
Stat2.3X Introduction To Statistics: Inference (97%)
Sabermetrics 101: Introduction To Baseball Analytics (99%)
Statistics In Medicine (95%)
Statistical Reasoning For Public Health: Estimation, Inference, & Interpretation (98%)
Mongodb For Developers (72%)
Bioinformatics: Introduction and Methods (95%)
Big Data In Education (100%)
Carlos Gamero Photo 2

Carlos Gamero

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Carlos Gamero Photo 3

Carlos Gamero

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Carlos Gamero Photo 4

Carlos Gamero

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Industry:
Semiconductors
Carlos Gamero Photo 5

Carlos Gamero

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Location:
United States
Carlos Gamero Photo 6

Carlos Gamero

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Carlos Gamero Photo 7

Carlos Gamero

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Business Records

Name / Title
Company / Classification
Phones & Addresses
Carlos Gamero
Managing
SHADYSIDE LLC
17611 Shadyside Cir, Lutz, FL 33549

Publications

Us Patents

Power Amplifier Control Technique For Enhanced Efficiency

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US Patent:
7193459, Mar 20, 2007
Filed:
Jun 23, 2004
Appl. No.:
10/874590
Inventors:
Darrell G. Epperson - Oak Ridge NC, US
Carlos Gamero - High Point NC, US
Ryan Bosley - Greensboro NC, US
Joel R. Gibson - Chandler AZ, US
Michael LaBelle - Phoenix AZ, US
Scott Yoder - Holly Springs NC, US
Assignee:
RF Micro Devices, Inc. - Greensboro NC
International Classification:
H03G 3/10
US Classification:
330130, 330133, 330134, 330296, 330297, 330310, 330267, 330223, 330261, 330285
Abstract:
A power amplifier configuration including power amplifier circuitry and power control circuitry and having improved Power Added Efficiency (PAE) is provided. The power amplifier circuitry includes one or more input amplifier stages in series with a final amplifier stage. The power control circuitry provides a variable supply voltage to the input amplifier stages based on an adjustable power control signal. The final amplifier stage is powered by a fixed supply voltage. In operation, as output power of the power amplifier is reduced from its highest power level, the variable supply voltage is reduced. Accordingly, RF power of an amplified signal provided to the final amplifier stage from the input amplifier stages decreases, and the final amplifier stage transitions from saturation to linear operation, thereby increasing the gain of the final amplifier stage. Thus, a desired output level can be maintained while operating at lower current levels.

Unlatch Feature For Latching Esd Protection Circuit

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US Patent:
7929263, Apr 19, 2011
Filed:
Aug 1, 2007
Appl. No.:
11/832114
Inventors:
Nathaniel Peachey - Oak Ridge NC, US
Carlos Gamero - High Point NC, US
Assignee:
RF Micro Devices, Inc. - Greensboro NC
International Classification:
H02H 9/00
US Classification:
361 56
Abstract:
The present invention is a latching electrostatic discharge (ESD) protection circuit that enables and latches an ESD clamping circuit upon an ESD event, and disables and un-latches the ESD clamping circuit upon either a drop in the DC supply voltage below a defined threshold or a time-out. The time-out protects against effects of inadvertent latching or any anomaly in which the latching ESD clamping circuit does not un-latch. An ESD event is a voltage spike between the DC supply voltage and ground wherein the ESD clamping circuit applies a low impedance between the DC supply voltage and ground to dissipate the energy contained in the voltage spike, thereby protecting adjacent circuitry.

Temperature Compensated Power Amplifier Power Control

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US Patent:
20050088237, Apr 28, 2005
Filed:
Oct 22, 2003
Appl. No.:
10/692075
Inventors:
Carlos Gamero - High Point NC, US
Ryan Bosley - Greensboro NC, US
Assignee:
RF MICRO DEVICES, INC. - Greensboro NC
International Classification:
H03F003/04
US Classification:
330289000
Abstract:
The present invention provides temperature compensation for a power amplifier by varying a supply voltage applied to the power amplifier. The supply voltage is varied based on operating temperature in light of the temperature characteristics of the power amplifier. Thus, the variation in the supply voltage offsets variations in the characteristics of the power amplifier due to changes in temperature. Whether the power amplifier is used to control the output power of a transmitter or as part of a polar modulation system, temperature compensation of the power amplifier allows the power amplifier to provide an accurate and repeatable output signal having essentially no fluctuations due to changes in temperature.
Carlos R Gamero from Lutz, FL, age ~51 Get Report