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Carlo M Gamboa

from San Lorenzo, CA
Age ~52
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Also known as:
Carlo Melendez Gamboa
Phone and address:
1233 Bockman Rd UNIT 39, San Lorenzo, CA 94580
(408) 547-7193
Related to:
Maricris Gamboa, 53
Connected to:
Alejandro Gamboa, 48Amalia Gamboa, 69Angela G Gamboa, 50Armando Gamboa, 56Blas Gamboa, 82Brad D Gamboa, 42Briana J Gamboa, 39Candida O Gamboa, 31Carmela Gamboa, 53Cindy Z Gamboa, 53

Carlo Gamboa Phones & Addresses

  • 1233 Bockman Rd UNIT 39, San Lorenzo, CA 94580 (408) 547-7193
  • San Jose, CA
  • 1267 Ternura Loop, Milpitas, CA 95035 (408) 945-8574
  • Santa Clara, CA

Resumes

Resumes

Carlo Gamboa Photo 1

Principal Engineer

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Location:
3901 north 1St St, San Jose, CA 95113
Industry:
Semiconductors
Work:
Cypress Semiconductor Corporation Jun 1998 - Aug 2001
Staff Packaging Engineer
Cypress Semiconductor Corporation Jun 1998 - Aug 2001
Principal Engineer - Npi Package and Assembly at Cypress Semiconductor Usa
Texas Instruments Dec 1993 - Jun 1998
New Product Development Engineer
Texas Instruments Sep 1994 - May 1996
Process Breakthrough Engineer
Texas Instruments Mar 1994 - Aug 1994
Mold Process Engineer
Education:
Saint Louis University 1988 - 1993
Bachelors, Bachelor of Science In Electrical Engineering, Electrical Engineering Saint Louis Hs 1984 - 1988
Skills:
Semiconductor Industry
Spc
Failure Analysis
Design For Manufacturing
Engineering Management
Manufacturing Engineering
Design of Experiments
Product Engineering
Assembly Processes
Fmea
Wafer Level Packaging
Molding and Encapsulation
Factory Automation
Packaging Engineering
Semiconductor Equipment
Electronics
Semiconductors
Interests:
Children
Economic Empowerment
Environment
Education
Poverty Alleviation
Science and Technology
Disaster and Humanitarian Relief
Animal Welfare
Health
Languages:
English
Filipino
Carlo Gamboa Photo 2

Carlo Gamboa

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Publications

Us Patents

Warpage-Compensating Die Paddle Design For High Thermal-Mismatched Package Construction

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US Patent:
8017445, Sep 13, 2011
Filed:
May 15, 2007
Appl. No.:
11/803475
Inventors:
Bo Chang - Cupertino CA, US
Carlo Gamboa - Milpitas CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H01L 23/495
H01L 21/60
US Classification:
438123, 257669, 257E23037, 257E21504, 257E21506, 257678
Abstract:
A method and packaging for semiconductor devices and integrated circuits is disclosed that eliminates warpage stress on packages caused by coefficient of thermal expansion (CTE) mismatch between the device, lead frame or die paddle and a molding compound. Generally, the method includes steps of: (i) mounting the die on which the device is fabricated to a die paddle of a leadframe; and (ii) encapsulating the die on the die paddle and at least a portion of the leadframe in a molding compound, wherein a difference between a first volume of molding compound above a plane of the leadframe and a second volume of molding compound below the plane of the leadframe is sufficiently reduced to substantially eliminate warpage of the finished package due to mismatch of CTEs of the device, lead frame and packaging compound. The die paddle may be etched or reduced to facilitate molding compound flowing under the plane of the leadframe. Other embodiments are also disclosed.

Integrated Circuit Package And Packaging Method

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US Patent:
8106489, Jan 31, 2012
Filed:
May 27, 2008
Appl. No.:
12/154775
Inventors:
Carlo Gamboa - Milpitas CA, US
Salvador Padre - Cavite, PH
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H01L 23/48
US Classification:
257666, 438612, 438108, 257693
Abstract:
A package and packaging method are provided that enable packaging of larger dies and/or smaller packages. Generally, the method includes steps of: (i) reducing a thickness of a portion of a top surface of leads of a leadframe extending into a package being formed; (ii) mounting a die to a paddle of the leadframe, the die extending past an edge of the paddle into a space created by reducing the thickness of the leads; and (iii) encapsulating the die and leadframe, including the reduced portion of the leads, in a molding compound. In one embodiment, the leads are reduced by half-etching the portion of the top surface. Preferably, the method further includes wire bonding pads on the die to etched portions of the leads to electrically couple the die to the leads. Alternatively, wire bonding is between the pads and non-etched portions of the leads. Other embodiments are also disclosed.

Flip-Flop Semiconductor Device Packaging Using Bent Leadfingers

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US Patent:
8283772, Oct 9, 2012
Filed:
Mar 30, 2007
Appl. No.:
11/731056
Inventors:
Carlo Gamboa - Milpitas CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H01L 21/00
US Classification:
257700, 257666, 257669
Abstract:
A semiconductor device package, a method of fabricating a semiconductor device package and a method of testing an integrated circuit utilizing a semiconductor device package are disclosed. Embodiments create a flip-flop semiconductor device package by coupling a semiconductor device, with a wire-bonded arrangement of conductive pads, in a face-up orientation beneath multiple bent leadfingers. The flip-flop package offers improved signaling properties, durability, reliability, and package density at reduced cost given that the conductive pads of the device couple directly to the bent leadfingers, without requiring the manufacture of a new device or the rerouting of signal paths. Additionally, the flip-flop configuration provides convenient means for exposing surfaces of the device (e. g. , to increase heat transfer therefrom, thermal performance of the device, etc. ) and/or surfaces of the leadfingers (e. g.

Multiple Die Paddle Leadframe And Semiconductor Device Package

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US Patent:
8436460, May 7, 2013
Filed:
Aug 20, 2007
Appl. No.:
11/894513
Inventors:
Carlo Gamboa - Milpitas CA, US
Bo Chang - Cupertino CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H01L 23/48
US Classification:
257692, 438123, 257E23031
Abstract:
A leadframe and semiconductor device package with multiple semiconductor device die paddles for accepting multiple semiconductor devices is disclosed, wherein the leadframe increases semiconductor device density and reduces cost by integrating the multiple dies into a semiconductor device package with a relatively small footprint. The leadframe may include at least one full-metal die paddle and at least one reduced-metal die paddle, which may form a unified or hybrid die paddle. The leadframe may enable electrical coupling of multiple semiconductor devices to a common leadfinger and/or die paddle, where internal leadfingers coupled to the common leadfingers and/or die paddles may receive the electrical coupling means from the semiconductor device. Surfaces of one or more die paddles of the leadframe may be exposed to the outside of the semiconductor device package to enable electrical testing of and/or provide heat dissipation from one or more of the semiconductor devices attached to the leadframe.

Optical Sensor Using A Laser Mounted On Top Of A Semiconductor Die

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US Patent:
20070206650, Sep 6, 2007
Filed:
Mar 5, 2007
Appl. No.:
11/682161
Inventors:
Karthik Ranganathan - Santa Clara CA, US
Gary Gibbs - San Jose CA, US
Carlo Gamboa - Milpitas CA, US
International Classification:
H01S 3/00
US Classification:
372 3805
Abstract:
A semiconductor device comprising an integrated circuit die and an electronic component mounted to the integrated circuit dies wherein the electronic component comprises a light emitting active area arranged to emit light.

Integrated Circuit Package With Electrically Isolated Leads

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US Patent:
7608914, Oct 27, 2009
Filed:
Apr 12, 2006
Appl. No.:
11/403409
Inventors:
Brett Alan Spurlock - Los Altos CA, US
Carlo Melendez Gamboa - Milpitas CA, US
Bo Soon Chang - Cupertino CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H01L 23/495
US Classification:
257666, 257672, 257676
Abstract:
In one embodiment, an integrated circuit package includes a lead frame with a die paddle and several leads. Portions of the lead frame not having an external electrical connection may be thinned such that they may be encapsulated by an electrically insulating packaging material on the back of the lead frame. Portions of the lead frame having external electrical connections may have a thickness such that they are exposed through the packaging material. The lead frame may be covered by an electrically insulating cover to protect components on the lead frame from erroneous electrical contact or electrostatic discharge (ESD) damage.
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Carlo M Gamboa from San Lorenzo, CA, age ~52 Get Report