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Carl James D'Acosta

from Gilbert, AZ
Age ~40

Carl D'Acosta Phones & Addresses

  • Gilbert, AZ
  • Franklin, WI
  • Mesa, AZ
  • Maricopa, AZ

Publications

Us Patents

Stacked Device Assembly With Integrated Coil And Method Of Forming Same

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US Patent:
7868729, Jan 11, 2011
Filed:
Mar 3, 2009
Appl. No.:
12/397112
Inventors:
James Jen-Ho Wang - Phoenix AZ, US
Carl E. D'Acosta - Mesa AZ, US
Justin E. Poarch - Gilbert AZ, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01F 5/00
US Classification:
336223, 336200, 336232, 296021
Abstract:
A stacked semiconductor device assembly () includes a device () having conductive traces () formed therein, and conductive interconnects () electrically connected to the conductive traces (). Another device () has conductive traces () formed therein and device pads () formed on an outer surface () of the device (). A method () entails attaching () a magnetic core () to an outer surface () of the device () and forming () the conductive interconnects () on the outer surface () using a stud bumping technique such that the interconnects () surround the magnetic core (). The conductive interconnects () are coupled () with the device pads () using thermocompression bonding to couple the device () with the device () to form a continuous device coil () wrapped around the magnetic core () from an alternating electrical connection of the traces (), the conductive interconnects (), and the traces ().

Micro-Electro-Mechanical Systems Device And Integrated Circuit Device Integrated In A Three-Dimensional Semiconductor Structure

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US Patent:
20080128901, Jun 5, 2008
Filed:
Nov 30, 2006
Appl. No.:
11/606739
Inventors:
Peter Zurcher - Phoenix AZ, US
Carl E. D'Acosta - Mesa AZ, US
Thomas P. Remmel - Mesa AZ, US
International Classification:
H01L 23/538
H01L 21/50
H01L 23/64
US Classification:
257724, 438455, 257415, 438456, 438107, 257E21499, 257E23173
Abstract:
Semiconductor devices (, and ) including an integrated circuit (IC) device () coupled to a micro-electro-mechanical systems (MEMS) device () and a method () for producing same are disclosed. The IC device includes a die seal ring () and the MEMS device includes a MEMS seal ring (), and the IC device is coupled to the MEMS device via the die seal ring and the MEMS seal ring. The MEMS device may include one or more passive devices () coupled to it. Moreover, a substrate () including an aperture () may be coupled to the passive device, wherein the aperture enables the passive device to be trimmed after being disposed on the MEMS device. The semiconductor devices include an RF signal path () and at least one other signal path ( and ), wherein the other signal path(s) may be an analog and/or a digital signal path.

Ion Implanter With Beam Resolving Apparatus And Method For Implanting Ions

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US Patent:
53069200, Apr 26, 1994
Filed:
Nov 23, 1992
Appl. No.:
7/980062
Inventors:
Jerry S. King - Chandler AZ
Carl E. D'Acosta - Mesa AZ
Craig L. Jasper - Phoenix AZ
Dan A. Banks - Phoenix AZ
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01J 3709
US Classification:
25049221
Abstract:
An ion implantation apparatus including a resolving aperture-shutter assembly (31) placed in the ion beam path (18). The resolving aperture-shutter assembly includes a movable shutter (34) and a shutter housing surrounding the movable shutter (34). Selected ions in an ion beam path (18) pass through a hole (44) in movable shutter (34) when the movable shutter (34) is in a first position, and are blocked by the solid surfaces when the movable shutter (34) is in a second position. The enclosure (32, 33, 39) completely surrounds the movable shutter (34). The enclosure (32, 33, 39) includes a first aperture (42) aligned with the ion beam path (18) for allowing the selected ions to enter the enclosure and a second aperture (41) aligned with the ion beam path (18) for allowing the selected ions to exit the enclosure after passing through the hole (44) in the movable shutter.

Method Of Etching A Semiconductor Substrate

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US Patent:
58519289, Dec 22, 1998
Filed:
Nov 27, 1995
Appl. No.:
8/562865
Inventors:
Jerry D. Cripe - Tempe AZ
Jerry L. White - Glendale AZ
Carl E. D'Acosta - Mesa AZ
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 21302
US Classification:
438748
Abstract:
A method of etching a semiconductor substrate (11) includes thinning (102) the semiconductor substrate (11), providing (103) a support layer (30) for the semiconductor substrate (11), providing (104) an etch mask (28) over the semiconductor substrate (11), and etching (105) the semiconductor substrate (11) using an etchant mixture of hydrofluoric acid, nitric acid, phosphoric acid, sulfuric acid, and a wetting agent at a temperature below ambient. The method is capable of using one etch step (105) and one etch mask (28) to form a plurality of trenches (12, 13) having the same width (15, 17) but different depths (16, 18) and different orientations. The method can be used to singulate different sizes and configurations of semiconductor dice from the semiconductor substrate (11).

Microelectronic Components Having Integrated Heat Dissipation Posts And Systems Including The Same

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US Patent:
20190206759, Jul 4, 2019
Filed:
Mar 7, 2019
Appl. No.:
16/295962
Inventors:
- Austin TX, US
Mahesh K. Shah - Scottsdale AZ, US
Lu Li - Gilbert AZ, US
David Abdo - Scdottsdale AZ, US
Geoffrey Tucker - Tempe AZ, US
Carl Emil D'Acosta - Mesa AZ, US
Jaynal A. Molla - Gilbert AZ, US
Justin Eugene Poarch - Gilbert AZ, US
Paul Hart - Phoenix AZ, US
International Classification:
H01L 23/367
H01L 21/48
H01L 23/13
H01L 23/528
H01L 23/00
Abstract:
Microelectronic systems and components having integrated heat dissipation posts are disclosed, as are methods for fabricating such microelectronic systems and components. In various embodiments, the microelectronic system includes a substrate having a frontside, a socket cavity, and inner cavity sidewalls defining the socket cavity. A microelectronic component is seated on the frontside of the substrate such that a heat dissipation post, which projects from the microelectronic component, is received in the socket cavity and separated from the inner cavity sidewalls by a peripheral clearance. The microelectronic system further includes a bond layer contacting the inner cavity sidewalls, contacting an outer peripheral portion of the heat dissipation post, and at least partially filling the peripheral clearance.

Air Cavity Packages And Methods For The Production Thereof

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US Patent:
20180082915, Mar 22, 2018
Filed:
Sep 19, 2016
Appl. No.:
15/269629
Inventors:
- AUSTIN TX, US
JAYNAL A. MOLLA - GILBERT AZ, US
DAVID ABDO - SCOTTSDALE AZ, US
MALI MAHALINGAM - SCOTTSDALE AZ, US
CARL D'ACOSTA - MESA AZ, US
Assignee:
FREESCALE SEMICONDUCTOR INC. - AUSTIN TX
International Classification:
H01L 23/20
H01L 23/047
H01L 21/48
H01L 23/057
H01L 23/367
B22F 3/10
B22F 1/00
B23K 35/02
B23K 35/30
Abstract:
Air cavity packages and methods for producing air cavity packages containing sintered bonded components, multipart window frames, and/or other unique structural features are disclosed. In one embodiment, a method for fabricating an air cavity package includes the step or process of forming a first metal particle-containing precursor layer between a base flange and a window frame positioned over the base flange. A second metal particle-containing precursor layer is further formed between the base flange and a microelectronic device positioned over the base flange. The metal particle-containing precursor layers are sintered substantially concurrently at a maximum processing temperature less than melt point(s) of metal particles within the layers to produce a first sintered bond layer from the first precursor layer joining the window frame to the base flange and to produce a second sintered bond layer from the second precursor layer joining the microelectronic device to the base flange.

Die-To-Die Inductive Communication Devices And Methods

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US Patent:
20150001948, Jan 1, 2015
Filed:
Jun 28, 2013
Appl. No.:
13/930236
Inventors:
Fred T. BRAUCHLER - Canton MI, US
John M. PIGOTT - Phoenix AZ, US
Darrel R. FREAR - Phoenix AZ, US
Vivek GUPTA - Phoenix AZ, US
Randall C. GRAY - Tempe AZ, US
Norman L. OWENS - Sun Lakes AZ, US
Carl E. D'ACOSTA - Mesa AZ, US
International Classification:
H01L 25/065
H02J 5/00
H01L 25/00
US Classification:
307104, 257506, 438109
Abstract:
Embodiments of inductive communication devices include first and second galvanically isolated IC die and a dielectric structure. Each IC die has a coil proximate to a first surface of the IC die. The IC die are arranged so that the first surfaces of the IC die face each other, and the first coil and the second coil are aligned across a gap between the first and second IC die. The dielectric structure is positioned within the gap directly between the first and second coils, and a plurality of conductive structures are positioned in or on the dielectric structure and electrically coupled with the second IC die. The conductive structures include portions configured to function as bond pads, and the bond pads may be coupled to package leads using wirebonds. During operation, signals are conveyed between the IC die through inductive coupling between the coils.

Die-To-Die Inductive Communication Devices And Methods

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US Patent:
20150004902, Jan 1, 2015
Filed:
Jun 28, 2013
Appl. No.:
13/930250
Inventors:
John M. Pigott - Phoenix AZ, US
Fred T. Brauchler - Canton MI, US
Darrel R. Frear - Phoenix AZ, US
Vivek Gupta - Phoenix AZ, US
Randall C. Gray - Tempe AZ, US
Norman L. Owens - Sun Lakes AZ, US
Carl E. D'Acosta - Mesa AZ, US
International Classification:
H04B 5/00
H01L 49/02
US Classification:
455 411, 257531, 438 3
Abstract:
Embodiments of inductive communication devices include first and second galvanically isolated IC die. The first IC die has a first coil proximate to a first surface of the first IC die, and the second IC die has a second coil proximate to a first surface of the second IC die. The first and second IC die are arranged so that the first surfaces of the first and second IC die face each other, and the first coil and the second coil are aligned across a gap between the first and second IC die. One or more dielectric components are positioned within the gap directly between the first and second coils. During operation, a first signal is provided to the first coil, and the first coil converts the signal into a time-varying magnetic field. The magnetic field couples with the second coil, which produces a corresponding second signal.
Carl James D'Acosta from Gilbert, AZ, age ~40 Get Report