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Byoungro So Phones & Addresses

  • San Ramon, CA
  • 3707 Poinciana Dr, Santa Clara, CA 95051 (408) 261-0755
  • Tarrytown, NY
  • 4734 Oakwood Ave, Los Angeles, CA 90004 (323) 466-2853
  • 4836 Hollow Corner Rd, Culver City, CA 90230 (310) 204-5543
  • Yorktown Heights, NY
  • 4734 Oakwood Ave APT 207, Los Angeles, CA 90004 (323) 816-3738

Work

Position: Building and Grounds Cleaning and Maintenance Occupations

Education

Degree: Graduate or professional degree

Emails

Publications

Us Patents

Compiler Implemented Software Cache In Which Non-Aliased Explicitly Fetched Data Are Excluded

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US Patent:
8214816, Jul 3, 2012
Filed:
May 28, 2008
Appl. No.:
12/128194
Inventors:
Tong Chen - Yorktown Heights NY, US
John Kevin Patrick O'Brien - South Salem NY, US
Kathryn O'Brien - South Salem NY, US
Byoungro So - Santa Clara CA, US
Zehra N. Sura - Yorktown Heights NY, US
Tao Zhang - Duluth GA, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 9/45
US Classification:
717157
Abstract:
A compiler implemented software cache in which non-aliased explicitly fetched data are excluded are provided. With the mechanisms of the illustrative embodiments, a compiler uses a forward data flow analysis to prove that there is no alias between the cached data and explicitly fetched data. Explicitly fetched data that has no alias in the cached data are excluded from the software cache. Explicitly fetched data that has aliases in the cached data are allowed to be stored in the software cache. In this way, there is no runtime overhead to maintain the correctness of the two copies of data. Moreover, the number of lines of the software cache that must be protected from eviction is decreased. This leads to a decrease in the amount of computation cycles required by the cache miss handler when evicting cache lines during cache miss handling.

Methods And Apparatus To Optimize The Parallel Execution Of Software Processes

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US Patent:
8316360, Nov 20, 2012
Filed:
Sep 29, 2006
Appl. No.:
11/537585
Inventors:
Byoungro So - Santa Clara CA, US
Anwar M. Ghuloum - Menlo Park CA, US
Youfeng Wu - Palo Alto CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 9/45
US Classification:
717159
Abstract:
Methods and apparatus to optimize the parallel execution of software processes are disclosed. An example method includes receiving a first software process that processes a set of data, locating a first primitive in the first software process, and decomposing the first primitive into a first set of one or more sub-primitives. The example methods and apparatus additionally perform static fusion and dynamic fusion to optimize software processes for execution in parallel processing systems.

Compiler Implemented Software Cache Apparatus And Method In Which Non-Aliased Explicitly Fetched Data Are Excluded

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US Patent:
20070261042, Nov 8, 2007
Filed:
Apr 14, 2006
Appl. No.:
11/279768
Inventors:
Tong Chen - Yorktown Heights NY, US
John O'Brien - South Salem NY, US
Kathryn O'Brien - South Salem NY, US
Byoungro So - Santa Clara CA, US
Zehra Sura - Yorktown Heights NY, US
Tao Zhang - Duluth GA, US
International Classification:
G06F 9/45
US Classification:
717148000
Abstract:
A compiler implemented software cache apparatus and method in which non-aliased explicitly fetched data are excluded are provided. With the mechanisms of the illustrative embodiments, a compiler uses a forward data flow analysis to prove that there is no alias between the cached data and explicitly fetched data. Explicitly fetched data that has no alias in the cached data are excluded from the software cache. Explicitly fetched data that has aliases in the cached data are allowed to be stored in the software cache. In this way, there is no runtime overhead to maintain the correctness of the two copies of data. Moreover, the number of lines of the software cache that must be protected from eviction is decreased. This leads to a decrease in the amount of computation cycles required by the cache miss handler when evicting cache lines during cache miss handling.

Compiler Assisted Re-Configurable Software Implemented Cache

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US Patent:
20080005473, Jan 3, 2008
Filed:
Jun 30, 2006
Appl. No.:
11/427790
Inventors:
Tong Chen - Yorktown Heights NY, US
John Kevin Patrick O'Brien - South Salem NY, US
Kathryn M. O'Brien - South Salem NY, US
Byoungro So - Santa Clara CA, US
Zehra N. Sura - Yorktown Heights NY, US
Tao Zhang - Duluth GA, US
International Classification:
G06F 12/00
US Classification:
711118
Abstract:
A computer implemented method, data processing system, and computer usable program code are provided for configuring a cache. A compiler performs an analysis of software code to identify cacheable information in the software code that will be accessed in the cache at runtime. The properties of the cacheable information are analyzed to form a data reference analysis. Using the data reference analysis, a cache configuration is determined for caching the cacheable information during execution of the software code. Modified lookup code is inserted in the software code based on the cache configuration used to configure the cache.
Byoungro D So from San Ramon, CA, age ~54 Get Report