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Bruno A Mattedi

from Woodland Park, CO
Age ~85
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Also known as:
Bruno Carolyn Mattedi, Allessio Mattedi Bruno
Phone and address:
1113 Kings Crown Rd, Woodland Park, CO 80863
(719) 687-8792
Related to:
Allan C Mackellar, 61Michael ReynoldsRobert MattediMattedi Allen, 59Devra D Goodwin, 51
Connected to:
Cecilia M Mattei, 35Chauncey M Mattei, 34Dave M Mattei, 36Dwaine A Mattei, 71Elena V Mattei, 61Emilio Mattei, 65Jo-Ann Mattei, 86Johnny L Mattei, 32Julian R Mattei, 29Kenneth J Mattei, 40

Bruno Mattedi Phones & Addresses

  • 1113 Kings Crown Rd, Woodland Park, CO 80863 (719) 687-8792
  • 8 Oriole Dr, Andover, MA 01810
  • Telluride, CO

Resumes

Resumes

Bruno Mattedi Photo 1

Tax Advisor

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Location:
1113 Kings Crown Rd, Woodland Park, CO 80863
Industry:
Retail
Work:
H&R Block
Tax Advisor
Habitat For Humanity of Teller County
Board of Directors
Education:
University of Colorado Boulder
Bruno Mattedi Photo 2

Bruno Mattedi

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Business Records

Name / Title
Company / Classification
Phones & Addresses
Bruno Mattedi
Bee Engineering LLC
Engineering Services
1113 Kings Crown Rd, Woodland Park, CO 80863
Bruno A. Mattedi
Manager
BEE ENGINEERING, LLC
8 Oriole Dr SUITE 201, Andover, MA 01810

Publications

Us Patents

Floating Point Arithmetic System And Method With Rounding Anticipation

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US Patent:
45625530, Dec 31, 1985
Filed:
Mar 19, 1984
Appl. No.:
6/591199
Inventors:
Bruno A. Mattedi - Andover MA
Hiromichi Watari - Somerville MA
Assignee:
Analogic Corporation - Wakefield MA
International Classification:
G06F 750
US Classification:
364745
Abstract:
A floating point arithmetic system with rounding anticipation including an arithmetic unit for arithmetically combining two mantissas; a carry circuit for determining whether the sum will overflow upon the addition of two mantissas and whether the difference will have a leading zero upon the subtraction of two mantissas; the subtrahend in subtraction and the augend in addition include guard, round, and sticky digits; a rounding circuit is responsive to the carry circuit for rounding the least significant digit of the sum when the sum will overflow and for designating for rounding the guard digit of the sum when the sum will not overflow, for designating for rounding the round digit of the difference when the difference will have a leading zero, and for designating for rounding the guard digit of the difference when the difference will not have a leading zero; and means for introducing to the arithmetic unit at the designated digit during the arithmetic combining of the two mantissas an amount equal to one-half the radix to effect the rounding during the arithmetic operation.

Full Floating Point Vector Processor With Dynamically Configurable Multifunction Pipelined Alu

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US Patent:
45890676, May 13, 1986
Filed:
May 27, 1983
Appl. No.:
6/498877
Inventors:
John B. Porter - Lexington MA
David W. Altmann - Marblehead MA
Bruno A. Mattedi - Andover MA
Ralph Jones - Waltham MA
Assignee:
Analogic Corporation - Peabody MA
International Classification:
G06F 1516
G06F 938
G06F 749
G06F 738
US Classification:
364200
Abstract:
A full floating point vector processor includes a master processing unit having DMA I/O means, a wide bandwidth data memory having static RAM and/or interleaved dynamic RAM, an address generator operative to provide address generation for data loaded in the data memory, a concurrently operating pipeline control sequencer operative to provide fully programmable horizontal format microinstructions synchronously with the addresses generated by the address generator, and a pipelined arithmetic and logical unit responsive to the addressed data and to the synchronously provided microinstructions and operative to evaluate one of a user selectable plurality of computationally intensive functions. The address generator, the pipeline controlsequencer, and the master processing unit are configured in parallel. The address generator includes means operative to provide pipeline input and output data dependent address generation.

Command Bus

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US Patent:
44620292, Jul 24, 1984
Filed:
Dec 6, 1979
Appl. No.:
6/100710
Inventors:
Leopold Neumann - Lexington MA
Gerald N. Shapiro - Newton MA
Bruno A. Mattedi - Andover MA
Assignee:
Analogic Corporation - Wakefield MA
International Classification:
H04Q 900
US Classification:
3408255
Abstract:
A system for reducing a fixed number of data buses and connections in a computer system having a number of modules connected to the data bus utilizing the internal circuits of the various processing units or modules to transmit data from one unit to another via the data bus when the normal function of a unit can be interrupted, with the data routing and module control being under the control of a command bus.
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Bruno A Mattedi from Woodland Park, CO, age ~85 Get Report