Bruce D Gavril

54148324, May 9, 1995

Dec 17, 1992

7/991930

Monty M. Denneau - Brewster NY
Bruce D. Gavril - Chappaqua NY
Peter H. Hochschild - New York NY
Craig B. Stunkel - Bethel CT

International Business Machines Corporation - Armonk NY

G06F 104

395550

A synchronous communication apparatus can be tuned to ensure reliable reception of signals propagating along transmission lines. The apparatus can be used as a communication port in a high frequency, highly connected synchronous network in which all ports can be tuned by a single, remote network control device. A local data source outputs a data signal during each of a series of local clock periods. A local source delay circuit receives input data signals from the local data source, and outputs output signals delayed by all amount (mT+. DELTA. pT) relative to corresponding input data signals, where m is a positive integer or zero, and where 0

47274778, Feb 23, 1988

Mar 22, 1985

6/714761

Bruce D. Gavril - Chappaqua NY

International Business Machines Corp. - Armonk NY

G06F 1340

364200

A transportable bus control architecture for single-chip microprocessors consists of an interface control unit that is logically independent of the associated co-resident, common clock-driven microprocessing unit. This independence allows the interface control unit logic to be used with a variety of microprocessing units. The interface control unit presents an external appearance that is compatible with the peripheral devices of a specific microprocessor referred to as the "compatible microprocessor", thereby making available to an associated co-resident microprocessing unit the support devices of the compatible microprocessor. The interface control unit can also access other external devices not related and transparent to the devices of the compatible microprocessor. The interface control unit is logically divided into an execution section and a control section. The execution section is controlled by the control section and comprises various registers, latches, multiplexers, logic, and data and address paths that provide communication between the co-resident microprocessing unit and off-chip devices.

54147409, May 9, 1995

Dec 17, 1992

7/992200

Monty M. Denneau - Brewster NY
Bruce D. Gavril - Chappaqua NY
Peter H. Hochschild - New York NY
Craig B. Stunkel - Bethel CT

International Business Machines Corporation - Armonk NY

H04L 700

375371

A communication system segment having phase multiplexing. A first communication station contains a data source which sequentially outputs a series of data signals during a series of clock periods. The data source outputs one data signal from the series during each clock period. The first communication station also contains a transition buffer which has an input connected to the output of the data source. The transition buffer has a first-in, first-out mode in which the transition buffer stores a series of Q data signals output from the data source during the most recent Q clock periods, where Q is an integer greater than zero. A second communication station contains a data receiver which sequentially inputs a series of data signals during a series of clock periods. The data receiver inputs one data signal from the series during each clock period. A communication line connects the output of the data source to the input of the data receiver.

40042774, Jan 18, 1977

May 5, 1975

5/574585

Bruce D. Gavril - New York NY

G06F 304

3401725

Switching apparatus and methods are disclosed by which one or more secondary computers of a loosely-coupled multiprocessing system may communicate directly with selected items of active peripheral equipment of a main computer of the system. This invention, which is an improvement over device-sharing means and indirect-accessing methods of the prior art, may be applied to existing computer systems without modification to any element of their hardware and without modification to the operating system software of the main computer. An essentially autonomous "intelligent switch," connected to an input/output interface (bus) of each processor and completely transparent to the main processor, is used to switch one or more items of operating peripheral equipment from the main computer to a secondary computer in response to asynchronous service requests from the secondary computer. Two modes of operation are provided: Interface Capture and Data Capture. Interface Capture provides a means for temporarily borrowing items of peripheral equipment having off-line operating capabilities, such as buffered line-printers, and is performed during a normal off-line operation of such equipment.

53717333, Dec 6, 1994

Mar 4, 1993

8/026386

Monty M. Denneau - Brewster NY
Bruce D. Gavril - Chappaqua NY
Peter H. Hochschild - New York NY
Craig B. Stunkel - Bethel CT

International Business Machines Corporation - Armonk NY

H04J 116

370 17

For use by a particular node within a digital data communications network having a plurality of counter-synchronized nodes including the particular node, called the central service node (CSN), and at least one remote node, all nodes being clocked at a common frequency, each node being synchronized by its own nodal time counter and connected to at least one other node by at least one transmission segment that completes a transmission path from the CSN, method and apparatus for: (a) establishing any value of virtual transmission delay (vtd) at individual transmission segments; (b) non-destructively determining the existing vtd at individual transmission segments; and (c) establishing basal distributions of vtd throughout the network and determining the elements thereof, (a), (b), and (c) being achieved without the central service node knowing real transmission delay (rtd) and inter-nodal asynchrony anywhere within the network and without requiring the active participation of any remote node. Virtual transmission delay for a transmission segment is the algebraic difference between rtd and the asynchrony between its source and destination nodes. It is the fundamental parameter governing the synchronization of nodal counters and inter-nodal information transfer.