Brice J Feal

49244248, May 8, 1990

Apr 25, 1988

7/185759

Stamatis Vassiliadis - Vestal NY
Eric M. Schwarz - Endicott NY
Michael Putrino - Endicott NY
Brice J. Feal - Endicott NY

International Business Machines Corporation - Armonk NY

G06F 1110

364738

An apparatus for predicting parity of a result produced by selection of the most or least significant thirty-two bits produced by a thirty-four bit adder, the parity being predicted concurrently with and independently of the result. Parity for byte Si of the selected result is derived by circuitry implementing the relationship: Pi=yP(m,n-1) V P(n,m+7) V y'P(m+8, n+7) in which Pi is the parity bit for Si, y is the positive sense of a signal indicating selection, of the most significant thirty-two result bits, y' is the complement of y and indicates selection of the least significant thirty-two result bits, P(M,n-1) is parity over the two most significant result bits in the portion of the result covering result bits m through n+7, P(m+8, n+7) is parity of the two least significant bits of the result portion, P(n, m+7) is parity over the central bits of the portion, i is an integer and 0. ltoreq. i. ltoreq. 3, m=8i, and n=m+2.

49530810, Aug 28, 1990

Dec 21, 1988

7/288797

Brice J. Feal - Endicott NY
Donald J. Hanrahan - Endwell NY
David J. Shippy - Endwell NY

International Business Machines Corporation - Armonk NY

G06F 1314

364200

In a data bus system which links a plurality of users, user access to the bus is provided by an arbiter which responds to a plurality of user requests for bus access by employing an adjustable priority scheme for granting access. When a user has access to the bus, the arbiter updates user priority by assigning the lowest priority to the current user and upwardly adjusting the priorities of all currently-requesting users.

49244221, May 8, 1990

Feb 17, 1988

7/157500

Stamatis Vassiliadis - Vestal NY
Michael Putrino - Endicott NY
Ann E. Huffman - Johnson City NY
Brice J. Feal - Endicott NY
Gerald G. Pechanek - Endwell NY

International Business Machines Corporation - Armonk NY

G06F 738

36471509

The invention determines when two operands are equivalent directly from the operand without the use of an adder. In one embodiment, conditions for the sum being equal to zero are determined from half sum to carry and transmit operators derived from the input operands. These operands are used in some known types of adders and, thus may be provided from a parallel adder to the condition prediction circuitry. In another embodiment, the equations for a carry-save-adder are modified to provide a circuit specifically designed for the determination of the condition when the sum of the operands is equal to zero. This sum is equal to zero circuit greatly reduces the gate delay and gate count thus allowing the central processing unit to determine the condition prior to the actual sum of two operands. This allows the CPU to react to the condition more quickly, thus increasing overall system speed.

49473590, Aug 7, 1990

May 1, 1989

7/346147

Stamatis Vassiliadis - Vestal NY
Michael Putrino - Endicott NY
Ann E. Huffman - Johnson City NY
Brice J. Feal - Endicott NY
Gerald G. Pechanek - Endwell NY

International Business Machines Corporation - Armonk NY

G06F 738

36471509

The invention determines when two operands are equivalent directly from the operand without the use of an adder. In one embodiment, conditions for the sum being equal to zero are determined from half sum to carry and transmit operators derived from the input operands. These operands are used in some known types of adders and, thus may be provided from a parallel adder to the condition prediction circuitry. In another embodiment, the equations for a carry-save-adder are modified to provide a circuit specifically designed for the determination of the condition when the sum of the operands is equal to zero. This sum is equal to zero circuit greatly reduces the gate delay and gate count thus allowing the central processing unit to determine the condition prior to the actual sum of two operands. This allows the CPU to react to the condition more quickly, thus increasing overall system speed.