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Brian Soderberg Phones & Addresses

  • Rancho Mirage, CA
  • Cle Elum, WA
  • 407 Lake Sammamish Pkwy SE, Sammamish, WA 98074
  • Redmond, WA
  • Woodinville, WA
  • Bellevue, WA
  • Kiona, WA
  • 13524 184Th Ave NE, Woodinville, WA 98072 (360) 807-8925

Work

Company: Round two games 2015 Position: Owner

Education

School / High School: University of Washington 1974 to 1979

Skills

Video Games • Game Development • Game Design • Social Games • Online Gaming • Game Programming • Ps3 • Perforce • Monetization • Casual Games • Multiplayer • Console

Emails

l***g@scu.edu

Industries

Entertainment

Public records

Vehicle Records

Brian Soderberg

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Address:
407 E Lk Sammamish Pkwy SE, Sammamish, WA 98074
VIN:
5J6YH28727L013151
Make:
HONDA
Model:
ELEMENT
Year:
2007

Resumes

Resumes

Brian Soderberg Photo 1

Owner

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Location:
309 Loch Lomond Rd, Rancho Mirage, CA 92270
Industry:
Entertainment
Work:
Round Two Games
Owner

Zipper Interactive 1995 - 2014
President

Bbn Delta Graphics 1986 - 1994
Division Scientist
Education:
University of Washington 1974 - 1979
Mercer Island High School
Skills:
Video Games
Game Development
Game Design
Social Games
Online Gaming
Game Programming
Ps3
Perforce
Monetization
Casual Games
Multiplayer
Console

Business Records

Name / Title
Company / Classification
Phones & Addresses
Brian Soderberg
CTO, Co-founder And Chief Technology Officer
Zipper Interactive Inc
Software Publishers
8314 154 Ave NE, Redmond, WA 98052
(425) 861-6561
Brian T Soderberg
Vice President,Secretary
FLYUP, INC

Publications

Us Patents

Multiple-Level Occulting Using A Mask Buffer

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US Patent:
56196270, Apr 8, 1997
Filed:
May 3, 1994
Appl. No.:
8/237285
Inventors:
Brian T. Soderberg - Woodinville WA
Dale D. Miller - Seattle WA
Henrik Lind - Seattle WA
Richard Jarvis - Everett WA
Mark Kenworthy - Duvall WA
Assignee:
Loral Aerospace Corp. - New York NY
International Classification:
G06T 1510
US Classification:
395121
Abstract:
Occulting apparatus for use with an image generator that provides for multiple-level occulting of image data. The occulting apparatus comprises a mask buffer and control logic for processing image data to construct and store an obscurance mask in the mask buffer. Foreground entities contained in the image data are logically ORed into the mask buffer until the entities extend beyond a predefined range from a predetermined image viewpoint. Thereafter, the mask is used by the control logic to reject entities contained in subsequently processed image data that are fully obscured by the foreground entities comprising the obscurance mask. The control logic includes an obscurance manager, a region processor, an object processor, a polygon processor, and insertion logic. The obscurance manager is a controller for building and applying the obscurance mask to the image data. The region, object, and polygon processors respectively process regions, objects, and polygons in the image to determine if they are obscured, reject obscured entities, and transmits unobscured entities to subsequent processors.

Image Element Depth Buffering Using Two Buffers

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US Patent:
54715679, Nov 28, 1995
Filed:
Aug 8, 1991
Appl. No.:
7/741999
Inventors:
Brian T. Soderberg - Woodinville WA
Mark L. Kenworthy - Renton WA
Assignee:
Bolt Beranek and Newman Inc. - Cambridge MA
International Classification:
G06T 1700
US Classification:
395133
Abstract:
Depth buffered anti-aliasing in a real time image generation system utilizing two separate buffers, one for combining attributes of object pixel definitions which are of less than full coverage and another for storing the attributes of each new object pixel definition which is of full coverage and which is closer to the viewpoint than any attributes currently stored. If the depth value in the partial buffer is closer the viewpoint than that in the full buffer, a set of attributes is output which is a weighted mixture of those stored in the two buffers.

Image Generator Architecture Employing Tri-Level Fixed Interleave Processing And Distribution Buses

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US Patent:
54936438, Feb 20, 1996
Filed:
May 3, 1994
Appl. No.:
8/237286
Inventors:
Brian T. Soderberg - Woodinville WA
Dale D. Miller - Seattle WA
Douglas Pheil - Redmond WA
Kent Cauble - Renton WA
Mark N. Heinen - Issaquah WA
Mark L. Kenworthy - Duvall WA
Assignee:
Loral Aerospace Corp. - New York NY
International Classification:
G06F 1500
US Classification:
395162
Abstract:
An image generator architecture in which tri-level fixed interleave processing provides medium grain parallelism for polygon, tiling, and pixel operations. Input data at each stage are divided into spatially distributed subsets that are interleaved among parallel processors using a fixed, precalculated mapping that minimizes correlation of local scene complexity with any one processor. The present tri-level fixed interleave processing architecture divides a processing task into a pseudo-random, fixed interleaved pattern of regions that are assigned to different processors. Each processor processes many of these randomly located regions. The assignment of processors to regions is a fixed repeating pattern. The highest level of fixed interleave processing is the allocation of fixed-size database regions (area modules) to polygon processors. The next level relates to image sub-region fixed interleave processing.
Brian T Soderberg from Rancho Mirage, CA, age ~69 Get Report