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Borivoje H Nikolic

from Oakland, CA
Age ~57
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Also known as:
Borivoj Nikolic, Borivos Welty, E Welty
Phone and address:
8 Woodside Glen Ct, Oakland, CA 94602
(510) 530-2167
Related to:
Walter Nikolic, 32Aleksandra NikolicRichard B Welty, 74Rick B Welty, 74Charleen Welty, 45Jesse R Welty, 55Rebecca J Nikolic, 50Charleen H Welty
Connected to:
Alex J Nikolic, 36Alexandra M Nikolic, 56Bojana Nikolic, 39Branislava Nikolic, 79David A Nikolic, 55Filip Nikolic, 37Gary P Nikolich, 67George Nikolic, 106Gregory J Nikolich, 50Ina Nikolic, 46

Borivoje Nikolic Phones & Addresses

  • 8 Woodside Glen Ct, Oakland, CA 94602 (510) 530-2167
  • 240 Caldecott Ln, Oakland, CA 94618
  • San Jose, CA
  • 3001 Derby St, Berkeley, CA 94705
  • Alameda, CA
  • Davis, CA

Work

Company: B nikolic 2000 Position: Consultant

Education

Degree: Doctorates, Doctor of Philosophy School / High School: University of California, Davis 1996 to 1999

Industries

Semiconductors

Resumes

Resumes

Borivoje Nikolic Photo 1

Consultant

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
B Nikolic
Consultant
Uc Berkeley
Professor
Education:
University of California, Davis 1996 - 1999
Doctorates, Doctor of Philosophy University of Belgrade 1992 - 1994
University of Belgrade 1987 - 1992

Publications

Us Patents

Reduced-Complexity Sequence Detection

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US Patent:
6553541, Apr 22, 2003
Filed:
Apr 5, 2000
Appl. No.:
09/544241
Inventors:
Borivoje Nikolic - Berkeley CA
Leo Fu - San Jose CA
Michael Leung - Sunnyvale CA
Vojin G. Oklobdzija - Berkeley CA
Richard Yamasaki - late of Torrance CA
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H03M 1341
US Classification:
714795, 360 40
Abstract:
Reduction of the complexity of a Viterbi-type sequence detector is disclosed. It was based on elimination of less probably taken branches in the trellis. The method is applied to the design of the E PR4 channel with 8/9 rate sliding block trellis code. Coding, by itself eliminates two states by coding constraints, and the disclosed method reduces the number of required ACS units from 14 to 11, while reducing their complexity as well. For the implementation of E PR4 detection, 4 4-way, 3 3-way, 3 2-way and one 1-way ACSs are needed. System simulations show no BER performance drop at common SNRs when compared with a full 16-state E PR4 implementation in magnetic disk drives.

Sense Amplifier-Based Flip-Flop With Asynchronous Set And Reset

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US Patent:
6633188, Oct 14, 2003
Filed:
Feb 12, 1999
Appl. No.:
09/248957
Inventors:
Wenyan Jia - Milpitas CA
Borivoje Nikolic - San Jose CA
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H03K 312
US Classification:
327217, 327 52, 327212, 365205
Abstract:
A flip-flop including a first stage and a second stage. The first stage receives a pair of differential signals to generate a set and reset signal. The complement of the set and reset signal generates output signals Q and {overscore (Q)}รข. These signals have rising and falling transistors with the same delays for the Q signal and the {overscore (Q)} signal. The second stage has symmetrical pull-up and pull-down circuits.

Simplified Branch Metric And Method

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US Patent:
6704903, Mar 9, 2004
Filed:
Feb 18, 2000
Appl. No.:
09/507510
Inventors:
Michael Ming Tak Leung - Sunnyvale CA
Leo Ki Chun Fu - San Jose CA
Borivoje Nikolic - Berkeley CA
James Kar Shing Chiu - Sunnyvale CA
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H03M 1300
US Classification:
714796
Abstract:
A branch metric computation using limited bits by clipping the dynamic range and/or approximating the square of the difference between a sample value and the target value by a lookup table or piecewise linear with comparable slopes.

Finfet-Based Sram With Feedback

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US Patent:
20070183185, Aug 9, 2007
Filed:
Jan 11, 2007
Appl. No.:
11/622305
Inventors:
Zheng Guo - Berkeley CA, US
Sriram Balasubramanian - Berkeley CA, US
Radu Zlatanovici - Berkeley CA, US
Borivoje Nikolic - Oakland CA, US
Assignee:
THE REGENTS OF THE UNIVERSITY OF CALIFORNIA - Oakland CA
International Classification:
G11C 11/00
US Classification:
365156000
Abstract:
Intrinsic variations and challenging leakage control in current bulk-Si MOSFETs force undesired tradeoffs to be made and limit the scaling of SRAM circuits. Circuits and mechanisms are taught herein which improve leakage and noise margin in SRAM cells, such as those comprising either six-transistor (6-T) SRAM cell designs, or four-transistor (4-T) SRAM cell designs. The inventive SRAM cells utilize a feedback means coupling a portion of the storage node to a back-gate of an access transistor. Preferably feedback is coupled in this manner to both access transistors. SRAM cells designed with this built-in feedback achieve significant improvements in cell static noise margin (SNM) without area penalty. Use of the feedback scheme also results in the creation of a practical 4-T FinFET-based SRAM cell that achieves sub-100 pA per-cell standby current and offers similar improvements in SNM as the 6-T cell with feedback.

Sliding Block (Rate 8/9) Trellis Code For Magnetic Recording

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US Patent:
60812109, Jun 27, 2000
Filed:
May 13, 1998
Appl. No.:
9/076717
Inventors:
Borivoje Nikolic - San Jose CA
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H03M 700
US Classification:
341 59
Abstract:
A method and system for encoding user data bits for magnetic recording channels that produces a stationary trellis and that limits the burst error propagation to three user bytes. The input data bits are grouped into even bytes and odd bytes. The even bytes are encoded first into even codewords, then each of the odd bytes is encoded into odd codewords based on the even codeword for the even byte preceding each odd byte and on the even codeword for the even byte following each odd byte. The encoding eliminates the most common error events associated with Partial Response Maximum Likelihood channels by: (i) disallowing sequences of four consecutive ones in the codewords, (ii) allowing sequences of three consecutive ones to begin only on certain bit positions in certain codewords, (iii) allowing only certain beginning sequences and ending sequences for odd and even codewords in specific situations, and (iv) changing specific bits in the odd and even codewords based on disallowed codeword sequences.

Sense Amplifier Based Flip-Flop

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US Patent:
61078530, Aug 22, 2000
Filed:
Nov 9, 1998
Appl. No.:
9/189065
Inventors:
Borivoje Nikolic - San Jose CA
Wenyan Jia - Milpitas CA
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H03K 3356
US Classification:
327217
Abstract:
A flip-flop including a first stage and a second stage. The first stage receives a pair of differential signals to generate a set and reset signal. The complement of the set and reset signal generates output signals Q and Q. These signals have equal rising and falling transitions with the same delays for the Q signal and the Q signal. The second stage has symmetrical pull-up and pull-down circuits.

Isbn (Books And Publications)

Digital Integrated Circuits: A Design Perspective

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Author

Borivoje Nikolic

ISBN #

0130909963

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Borivoje H Nikolic from Oakland, CA, age ~57 Get Report