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Bhaskar Kumar

from San Jose, CA
Age ~45
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Also known as:
Fnu Bhaskar Kumar, Bhaskar Kumar Fnu, Fnu Bhaskarkumar
Phone and address:
814 Chagall Rd, San Jose, CA 95138
Related to:
Lakshmi Somakumar, 46Venkata Sekhar, 50Kunapuli KumarKunapuli Udaykumar, 49Kunapuli Udaykumar, 59Chandra K Sekhar, 50
Connected to:
Aashish O Kumar, 57Abhinab Kumar, 37Abhinandan Kumar, 29Ajaya Kumar, 43Akriti Kumar, 32Akshay KumarAlankar Kumar, 42Allison M Kumar, 47Amarendra Kumar, 66Amitesh Kumar, 41

Bhaskar Kumar Phones & Addresses

  • 814 Chagall Rd, San Jose, CA 95138
  • Santa Clara, CA
  • Sunnyvale, CA
  • Orlando, FL
  • Burbank, CA

Publications

Us Patents

Apparatus And Methods For Reducing Light Induced Damage In Thin Film Solar Cells

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US Patent:
20110263074, Oct 27, 2011
Filed:
Apr 22, 2010
Appl. No.:
12/765458
Inventors:
Amir Al-Bayati - San Jose CA, US
Yong K. Chae - San Ramon CA, US
Shuran Sheng - Cupertino CA, US
Bhaskar Kumar - Santa Clara CA, US
Eran Valfer - Dresden, DE
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 31/18
US Classification:
438 96, 118663, 257E31047, 257E31001
Abstract:
Apparatus and methods for forming a silicon-containing i-layer on a substrate for a thin film photovoltaic cell are disclosed. The apparatus includes a chamber body defining a processing region containing the substrate, a hydrogen source and a silane source coupled to a plasma generation region, an RF power source that applies power at a power level in the plasma generation region to generate a plasma and deposit the silicon-containing i-layer at a selected deposition rate to a selected thickness and a controller. The controller controls the power level and the deposition rate of the i-layer on the substrate such that the thin film solar cell exhibits light induced damage that conforms to a linear fit of the product of the RF power, the deposition rate and the selected thickness of the i-layer. In accordance with further aspects of the present invention, the controller controls the RF power and the deposition rate so that a product (x) of the RF power in watts, the deposition rate of the i-layer in nm per min and the thickness of the i-layer in nm is less than a predetermined number y and satisfies the equation y=5E11*x+3.3749 plus or minus a margin.

High Efficiency Solar Cell Device With Gallium Arsenide Absorber Layer

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US Patent:
20120080092, Apr 5, 2012
Filed:
Sep 30, 2011
Appl. No.:
13/250748
Inventors:
Kaushal K. Singh - Santa Clara CA, US
Robert Jan Visser - Menlo Park CA, US
Srikant Rao - Powai Mumba, IN
Bhaskar Kumar - Santa Clara CA, US
Claire J. Carmalt - Rickmansworth Hertfordshire, GB
Ranga Rao Arnepalli - Veeravalli Andhrapradesh, IN
Omkaram Nalamasu - San Jose CA, US
Gaurav Saraf - Santa Clara CA, US
Sanjayan Sathasivam - Finchley, GB
Christopher Stuart Blackman - Marlow, GB
Assignee:
APPLIED MATERIALS, INC. - Santa Clara CA
International Classification:
H01L 31/0264
H01L 31/18
B82Y 40/00
US Classification:
136262, 438 94, 977842, 257E31004
Abstract:
Embodiments of the invention provide a method of forming a doped gallium arsenide based (GaAs) layer from a solution based precursor. The doped gallium arsenide based (GaAs) layer formed from the solution based precursor may assist solar cell devices to improve light absorption and conversion efficiency. In one embodiment, a method of forming a solar cell device includes forming a first layer with a first type of dopants doped therein over a surface of a substrate, forming a GaAs based layer on the first layer, and forming a second layer with a second type of dopants doped therein on the GaAs based layer.

Gallium Arsenide Based Materials Used In Thin Film Transistor Applications

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US Patent:
20120080753, Apr 5, 2012
Filed:
Sep 30, 2011
Appl. No.:
13/250766
Inventors:
Kaushal K. Singh - Santa Clara CA, US
Robert Jan Visser - Menlo Park CA, US
Bhaskar Kumar - Santa Clara CA, US
Assignee:
APPLIED MATERIALS, INC. - Santa Clara CA
International Classification:
H01L 29/786
H01L 21/20
H01L 21/336
US Classification:
257347, 438151, 438478, 257E29273, 257E21409, 257E2109
Abstract:
Embodiments of the invention provide a method of forming a group III-V material utilized in thin film transistor devices. In one embodiment, a gallium arsenide based (GaAs) layer with or without dopants formed from a solution based precursor may be utilized in thin film transistor devices. The gallium arsenide based (GaAs) layer formed from the solution based precursor may be incorporated in thin film transistor devices to improve device performance and device speed. In one embodiment, a thin film transistor structure includes a gate insulator layer disposed on a substrate, a GaAs based layer disposed over the gate insulator layer, and a source-drain metal electrode layer disposed adjacent to the GaAs based layer.

High Quality Tco-Silicon Interface Contact Structure For High Efficiency Thin Film Silicon Solar Cells

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US Patent:
20100051098, Mar 4, 2010
Filed:
Jun 9, 2009
Appl. No.:
12/481175
Inventors:
Shuran Sheng - Santa Clara CA, US
Yong Kee Chae - Pleasanton CA, US
Stefan Klein - Aschaffenburg, DE
Amir Al-Bayati - San Jose CA, US
Bhaskar Kumar - Santa Clara CA, US
Assignee:
APPLIED MATERIALS, INC. - Santa Clara CA
International Classification:
H01L 31/00
H01L 31/18
US Classification:
136256, 438 96, 257E2109
Abstract:
A method and apparatus for forming solar cells is provided. In one embodiment, a photovoltaic device includes a first TCO layer disposed on a substrate, a second TCO layer disposed on the first TCO layer, and a p-type silicon containing layer formed on the second TCO layer. In another embodiment, a method of forming a photovoltaic device includes forming a first TCO layer on a substrate, forming a second TCO layer on the first TCO layer, and forming a first p-i-n junction on the second TCO layer.

Cfx Layer To Protect Aluminum Surface From Over-Oxidation

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US Patent:
20220178017, Jun 9, 2022
Filed:
Dec 3, 2020
Appl. No.:
17/110785
Inventors:
- Santa Clara CA, US
Vinayak Vishwanath HASSAN - San Francisco CA, US
Bhaskar KUMAR - San Jose CA, US
Ganesh BALASUBRAMANIAN - Fremont CA, US
International Classification:
C23C 16/26
H01L 21/02
C23C 16/505
C23C 16/455
Abstract:
In one example, a method includes flowing a carbon-containing gas into a processing volume of a process chamber, the process chamber having internal surfaces comprising aluminum, and depositing a carbon film on the internal surfaces of the process chamber. The method also includes flowing fluorine radicals into the process chamber, and fluorinating the carbon film to create a CFlayer on the internal surfaces. The method also includes oxidizing the CFlayer on the internal surfaces creating an AlOCFlayer on the internal surfaces.

Carbon Cvd Deposition Methods To Mitigate Stress Induced Defects

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US Patent:
20220178026, Jun 9, 2022
Filed:
Dec 3, 2020
Appl. No.:
17/110774
Inventors:
- Santa Clara CA, US
Anup Kumar SINGH - Santa Clara CA, US
Bhaskar KUMAR - Santa Clara CA, US
International Classification:
C23C 16/455
C23C 16/26
C23C 16/505
H01L 21/02
Abstract:
A method includes flowing a carbon-containing precursor and a carrier gas into a processing volume having a substrate positioned therein, generating a plasma in the processing volume by applying a first RF bias to a substrate support to deposit a first portion of carbon film onto the substrate, and terminating flow of the carbon-containing precursor while maintaining flow of the carrier gas to maintain the plasma within the processing volume. The method also includes flowing a nitrogen-containing gas into the processing volume and ionizing the nitrogen-containing gas in the presence of the plasma, exposing the substrate having the carbon film thereon to the ionized nitrogen-containing gas for a time period less than three seconds, and terminating flow of the nitrogen-containing gas while maintaining the plasma and reintroducing the carbon-containing precursor into the processing volume in the presence of the plasma to deposit a second portion of the carbon film.

Stress Treatments For Cover Wafers

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US Patent:
20230069395, Mar 2, 2023
Filed:
Aug 30, 2021
Appl. No.:
17/460900
Inventors:
- Santa Clara CA, US
Bhaskar Kumar - Santa Clara CA, US
Meng Cai - Lynnfield MA, US
Sowjanya Musunuru - Milpitas CA, US
Andrew Nguyen - San Jose CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01J 37/32
H01L 21/02
B24B 7/22
C23C 16/44
Abstract:
Exemplary methods of manufacturing a semiconductor cover wafer may include sintering aluminum nitride particles into a substrate characterized by a thickness and characterized by a disc shape. The methods may include grinding a surface of the substrate to reduce the thickness to less than or about 2 mm. The methods may include polishing the surface of the substrate to reduce a roughness. The methods may include annealing the substrate at a temperature of greater than or about 800 C. for a time period of greater than or about 60 minutes.

Remote Capacitively Coupled Plasma Source With Improved Ion Blocker

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US Patent:
20210351020, Nov 11, 2021
Filed:
Jul 20, 2021
Appl. No.:
17/381162
Inventors:
- Santa Clara CA, US
Vinayak Vishwanath Hassan - Santa Clara CA, US
Bhaskar Kumar - Santa Clara CA, US
Ganesh Balasubramanian - Fremont CA, US
International Classification:
H01J 37/32
Abstract:
Apparatus and methods for generating a flow of radicals are provided. An ion blocker is positioned a distance from a faceplate of a remote plasma source. The ion blocker has openings to allow the plasma to flow through. The ion blocker is polarized relative to a showerhead positioned on an opposite side of the ion blocker so that there are substantially no plasma gas ions passing through the showerhead.
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Bhaskar Kumar from San Jose, CA, age ~45 Get Report