Barton J Sano

6912602, Jun 28, 2005

Oct 11, 2002

10/269666

Barton J. Sano - Fremont CA, US
Koray Oner - Sunnyvale CA, US
Laurent R. Moll - Satatoga CA, US
Manu Gulati - Santa Clara CA, US

Broadcom Corporation - Irvine CA

G06F013/28

710 22, 710 52, 710 38, 709212, 709250

An apparatus includes a first interface circuit, a second interface circuit, a memory controller for configured to interface to a memory, and a packet DMA circuit. The first interface circuit is configured to couple to a first interface for receiving and transmitting packet data. Similarly, the second interface circuit is configured to couple to a second interface for receiving and transmitting packet data. The packet DMA circuit is coupled to receive a first packet from the first interface circuit and a second packet from the second interface circuit. The packet DMA circuit is configured to transmit the first packet and the second packet in write commands to the memory controller to be written to the memory. In some embodiments, a switch is coupled to the first interface circuit, the second interface circuit, and the packet DMA circuit.

6941406, Sep 6, 2005

Jun 4, 2004

10/861624

Barton J. Sano - Fremont CA, US
Joseph B. Rowlands - Santa Clara CA, US
James B. Keller - Palo Alto CA, US
Laurent R. Moll - Saratoga CA, US
Koray Oner - Sunnyvale CA, US
Manu Gulati - Santa Clara CA, US

Broadcom Corporation - Irvine CA

G06F013/36
G06F013/14

710306, 710305, 710 22, 710 5

An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.

7206879, Apr 17, 2007

Oct 11, 2002

10/269922

Barton J. Sano - Fremont CA, US
Joseph B. Rowlands - Santa Clara CA, US
Laurent R. Moll - Saratoga CA, US
Manu Gulati - Santa Clara CA, US

Broadcom Corporation - Irvine CA

G06F 13/42
G06F 13/14
G06F 13/36
G06F 12/00

710105, 710305, 710308, 711141

An apparatus may include a first system and a second system. The first system includes a first plurality of interface circuits, and each of the first plurality of interface circuits is configured to couple to a separate interface. The second system includes a second plurality of interface circuits, and each of the second plurality of interface circuits is configured to couple to a separate interface. A first interface circuit of the first plurality of interface circuits and a second interface circuit of the second plurality of interface circuits are coupled to a first interface. Both the first interface circuit and the second interface circuit are configured to communicate packets, coherency commands, and noncoherent commands on the first interface.

7227870, Jun 5, 2007

Oct 11, 2002

10/270016

Barton J. Sano - Fremont CA, US
Laurent R. Moll - Saratoga CA, US
Manu Gulati - Santa Clara CA, US

Broadcom Corporation - Irvine CA

H04L 12/56

370419, 375372, 370463

An integrated circuit includes receive circuits for receiving packets, transmit circuits for transmitting packets, a packet DMA circuit for communicating packets to and from a memory controller, and a switch for selectively coupling the receive circuits to transmit circuits. The integrated circuit may flexibly merge and split the packet streams to provide for various packet processing/packet routing functions to be applied to different packets within the packet streams. An apparatus may include two or more of the integrated circuits, which may communicate packets between respective receive and transmit circuits.

7366092, Apr 29, 2008

Oct 14, 2003

10/684871

Laurent Moll - Saratoga CA, US
Barton J. Sano - Fremont CA, US
Thomas Albert Petersen - San Francisco CA, US

Broadcom Corporation - Irvine CA

H04J 1/16
H04L 12/28

370218, 370422

A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a parallel routing scheme for calculating routing information for incoming packets. Using the programmable hash and route routing scheme, a hash and route circuit can be programmed for a variety of applications, such as routing, flow-splitting or load balancing.

7394823, Jul 1, 2008

Oct 11, 2002

10/270014

Barton J. Sano - Fremont CA, US

Broadcom Corporation - Irvine CA

H04L 12/56

370419, 370235, 711141

An apparatus includes a plurality of memories, a plurality of systems, and a switch interface circuit. Each of the plurality of systems includes a memory controller coupled to a respective one of the plurality of memories. Additionally, each of the plurality of systems is coupled to at least one other one of the plurality of systems. Each of the plurality of systems further includes one or more coherent agents configured to access the plurality of memories, and wherein the plurality of systems enforce coherency across the plurality of systems for at least some accesses. At least one of the plurality of systems is coupled to the switch interface circuit separate from the interconnection of the plurality of systems. The switch interface circuit is configured to interface the apparatus to a switch fabric.

7403525, Jul 22, 2008

Jan 31, 2003

10/356323

Barton Sano - Fremont CA, US
Laurent Moll - Saratoga CA, US
Manu Gulati - Santa Clara CA, US

Broadcom Corporation - Irvine CA

H04L 12/56

370392, 370466

According to the present invention, the multiple processor device determines routing for a plurality of data segments. In determining the routing, the multiple processor device first receives the plurality of data segments. The plurality of data segments include multiplexed data fragments from at least one of a plurality of virtual channels. Further, a data segment of the plurality of data segments corresponds to one of the multiplexed data fragments. The multiple processor device then applies at least one routing rule to one of the plurality of data segments to produce at least one result corresponding to the one of the plurality of data segments. The multiple processor device then interprets the at least one result to determine whether sufficient information is available to render a routing decision for the one of the plurality of data segments. When the multiple processor device determines that there is sufficient information to render a routing decision, the multiple processor device determines routing of the one of the plurality of data segments. When there is insufficient information to render a routing decision, the one of the plurality of data segments is stored in a buffer corresponding to a packet in which the one of the plurality of data segments was received.

7424561, Sep 9, 2008

Mar 13, 2007

11/717511

Barton J. Sano - Fremont CA, US
Joseph B. Rowlands - Santa Clara CA, US
Laurent R. Moll - Saratoga CA, US
Manu Gulati - Santa Clara CA, US

Broadcom Corporation - Irvine CA

G06F 13/42
G06F 13/14
G06F 13/36
G06F 12/00

710105, 710305, 710308, 711141

An apparatus may include a first system and a second system. The first system includes a first plurality of interface circuits, and each of the first plurality of interface circuits is configured to couple to a separate interface. The second system includes a second plurality of interface circuits, and each of the second plurality of interface circuits is configured to couple to a separate interface. A first interface circuit of the first plurality of interface circuits and a second interface circuit of the second plurality of interface circuits are coupled to a first interface. Both the first interface circuit and the second interface circuit are configured to communicate packets, coherency commands, and noncoherent commands on the first interface.