Baoliang Zeng

Intel Corporation - Synapse Design
Santa Clara, CA
2013 to 2014
Technical Lead
LSI Corporation - Synapse Design
San Jose, CA
2012 to 2013
Technical Lead
Huawei/Hisilicon - Synapse Design
San Jose, CA
2011 to 2012
Technical Lead
Cypress Semiconductor
San Jose, CA
2010 to 2011
Principal Consulting Engineer
Verisilicon Inc

2009 to 2010
Principal Design Lead
Broadcom Corporation
Santa Clara, CA
2007 to 2009
Principal Design Engineer, 2 large complex 1.2GHz
Juniper Networks
Sunnyvale, CA
2006 to 2007
Sr. Staff Engineer
Sun Microsystems
Sunnyvale, CA
2003 to 2006
Staff Engineer, Design Lead of Floating-point
Hewlett-Packard Company
Fort Collins, CO
2002 to 2002
Project Manager
Hewlett-Packard Company
Santa Clara, CA
2000 to 2002
Project Manager
Hewlett-Packard Company
Fort Collins, CO
1993 to 2002
Project Manager
Hewlett-Packard Company
Fort Collins, CO
2000 to 2000
Tech Contributor(Sr. Tech Lead)
Hewlett-Packard Company

1999 to 1999
Clock & Methodology, Library Curator & Clock Gater Owner
Hewlett-Packard Company

1998 to 1999
Lead Engineer, Itanium II Multimedia Unit (MMU) implementation
Hewlett-Packard Company

1998 to 1998
Lead Engineer, Itanium II Multimedia Unit (MMU) Investigation
Hewlett-Packard Company
Fort Collins, CO
1995 to 1996
Lead Engineer, Itanium II Front-side-bus (FSB) investigation
Hewlett-Packard Company
Fort Collins, CO
1993 to 1995
Member of Technical Staff
IBM Corporation, Microprocessor Design Center

1992 to 1993
Design Engineer, for IBM 200MHz

University of Missouri-Columbia
Columbia, MO
1992
MSEE in High-speed VLSI Logic & Circuit Design, CAE/CAD Tools, Computer Arithmetic, High-end Microprocessor Design, Solid State Devices GPA: 4.0/4.0

GHz Customized Clock Design, High-performance datapath IP Design, High-speed VLSI circuit design, Deep understanding of 28nm/20nm technology, Microarchitecture, RTL/constraint development, Chip-level integration, Physical design of high-speed & large/complex SOCs (>20M gates, GHz+, 18+ tapeout), Design methodology & flow