Search

Bahram Ahanin

from Beverly Hills, CA
Age ~70
Get Report
Also known as:
Baha Ahanin, Bram Ahanin
Phone and address:
912 N Whittier Dr, Beverly Hills, CA 90210
Connected to:
Uchenna Ahanonu, 42Ejem N Ahanotu, 72Ossy E Ahanotu, 70Arman M Ahari, 28Rachel E Ahari, 39Eitan Aharon, 47John H Aharon, 88Manny N Aharon, 69Ofer Aharon, 40Walker Aharon, 32

Bahram Ahanin Phones & Addresses

  • 912 N Whittier Dr, Beverly Hills, CA 90210
  • 2342 Octavia St, San Francisco, CA 94109 (415) 567-1899 (415) 921-3280
  • Williamsville, NY
  • Cupertino, CA
  • Mountain View, CA
  • San Jose, CA
  • 2342 Octavia St, San Francisco, CA 94109 (415) 717-0077

Work

Position: Protective Service Occupations

Education

Degree: Graduate or professional degree

Resumes

Resumes

Bahram Ahanin Photo 1

Independent Electrical/Electronic Engineering Professional

View page
Location:
San Francisco Bay Area
Industry:
Electrical/Electronic Manufacturing
Work:
Altera Corporation 1989 - 2007
VP Design Automation
Bahram Ahanin Photo 2

Bahram Ahanin

View page

Business Records

Name / Title
Company / Classification
Phones & Addresses
Bahram Ahanin
Managing
Pharmplast LLC
Development & Manufacturing · Development and Manufacturing · Business Services at Non-Commercial Site · Nonclassifiable Establishments
2373 Pacific Ave, San Francisco, CA 94115

Publications

Us Patents

Programmable Logic Array Integrated Circuits

View page
US Patent:
6759870, Jul 6, 2004
Filed:
Feb 20, 2003
Appl. No.:
10/372373
Inventors:
Richard G. Cliff - Santa Clara CA
Bahram Ahanin - Cupertino CA
Craig Schilling Lytle - Palo Alto CA
Francis B. Heile - Santa Clara CA
Bruce B. Pedersen - Santa Clara CA
Kerry Veenstra - Concord CA
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03K 19177
US Classification:
326 41, 326 38
Abstract:
A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks (âLABsâ). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

Variable Depth And Width Memory Device

View page
US Patent:
RE38651, Nov 9, 2004
Filed:
Jun 12, 1998
Appl. No.:
09/096917
Inventors:
Chiakang Sung - Milpitas CA
Wanli Chang - Saratoga CA
Joseph Huang - San Jose CA
Richard G. Cliff - Milpitas CA
L. Todd Cope - San Jose CA
Cameron R. McClintock - Mountain View CA
William Leong - San Francisco CA
James A. Watson - Santa Clara CA
Bahram Ahanin - Cupertino CA
Assignee:
Altera Corporation - San Jose CA
International Classification:
G06F 1200
US Classification:
711170, 711171, 711150, 36523002, 326 38, 326 39, 326 40, 326 41
Abstract:
A programmable variable depth and width random-access memory circuit is provided. The memory circuit contains rows and columns of memory cells for storing data. A row decoder is used to address individual rows of the memory cells. Column address circuitry receives a column address signal and a width and depth selection signal. A column decoder within the column address circuitry addresses one or more columns of memory cells of the RAM array based on the selected width of the array. The output of the column decoder is routed to the appropriate column or columns of memory cells by a pattern of fixed connections and a group of programmable multiplexers. The number of data output lines to which data signals are provided is determined by the selected width of the RAM array. The output circuitry contains a group of programmable demultiplexers and a routing array having a pattern of fixed connections suitable for passing data signals from the RAM array to the selected number of data output lines.

Programmable Logic Array Integrated Circuits

View page
US Patent:
6897679, May 24, 2005
Filed:
Jan 31, 2003
Appl. No.:
10/356691
Inventors:
Richard G. Cliff - Milpitas CA, US
L. Todd Cope - San Jose CA, US
Cameron R. Mc Clintock - Mountain View CA, US
William Leong - San Francisco CA, US
James A. Watson - Santa Clara CA, US
Joseph Huang - San Jose CA, US
Bahram Ahanin - Cupertino CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03K019/177
US Classification:
326 41, 326 38
Abstract:
A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks (“LABs”). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

Programmable Logic Array Integrated Circuits

View page
US Patent:
20020130681, Sep 19, 2002
Filed:
Aug 22, 2001
Appl. No.:
09/935792
Inventors:
Richard Cliff - Milpitas CA, US
L. Cope - San Jose CA, US
Cameron Mc Clintock - Mountain View CA, US
William Leong - San Francisco CA, US
James Watson - Santa Clara CA, US
Joseph Huang - San Jose CA, US
Bahram Ahanin - Cupertino CA, US
International Classification:
H03K019/177
US Classification:
326/041000
Abstract:
A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks (“LABs”). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

Programmable Logic Device Having Fast Programmable Logic Array Blocks And A Central Global Interconnect Array

View page
US Patent:
54732662, Dec 5, 1995
Filed:
Oct 18, 1994
Appl. No.:
8/324860
Inventors:
Bahram Ahanin - Cupertino CA
Janusz K. Balicki - San Jose CA
Khusrow Kiani - Oakland CA
William Leong - San Francisco CA
Bezhad Nouban - Fremont CA
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03K 19177
US Classification:
326 41
Abstract:
A programmable logic device has a number of dedicated global control input lines which interface directly with individual building blocks known as logic array blocks. These lines can be used for clocks, presets, clears, or output-enables. Other logic signal lines from the centrally located global interconnect array are selected through an array of multiplexers and then interface with the logic array block. A configuration array of multiplexers in the logic array block selects from among these inputs, generating local control input signals, the final functions of which are decided by further multiplexing at the macrocell level within the logic array block.

Programmable Logic Array Integrated Circuits

View page
US Patent:
58282297, Oct 27, 1998
Filed:
May 1, 1997
Appl. No.:
8/847004
Inventors:
Richard G. Cliff - Milpitas CA
L. Todd Cope - San Jose CA
Cameron McClintock - Mountain View CA
William Leong - San Francisco CA
James Allen Watson - Santa Clara CA
Joseph Huang - San Jose CA
Bahram Ahanin - San Francisco CA
Chiakang Sung - Milpitas CA
Wanli Chang - Saratoga CA
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03K 19177
US Classification:
326 40
Abstract:
A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors. A relatively large block of random access memory ("RAM") may be provided on the device for use as read-only memory ("ROM") or RAM during operation of the device to perform logic.

Programmable Logic Array Integrated Circuits

View page
US Patent:
54365759, Jul 25, 1995
Filed:
Aug 25, 1993
Appl. No.:
8/111693
Inventors:
Bruce B. Pedersen - San Jose CA
Richard G. Cliff - Milpitas CA
Bahram Ahanin - Cupertino CA
Craig S. Lytle - Mountain View CA
Francis B. Heile - Santa Clara CA
Kerry S. Veenstra - San Jose CA
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03K 19177
US Classification:
326 40
Abstract:
A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

Programmable Logic Array With Local And Global Conductors

View page
US Patent:
54851033, Jan 16, 1996
Filed:
Dec 15, 1994
Appl. No.:
8/356516
Inventors:
Bruce B. Pedersen - Santa Clara CA
Richard G. Cliff - Santa Clara CA
Bahram Ahanin - Cupertino CA
Craig S. Lytle - Palo Alto CA
Francis B. Heile - Santa Clara CA
Kerry S. Veenstra - Concord CA
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03K 19177
US Classification:
326 41
Abstract:
A programmable logic array integrated circuit has a plurality of programmable logic elements grouped into a plurality of mutually exclusive groups. Each group includes signal conductors uniquely associated with that group for conveying signals between the programmable logic elements in that group. Other signal conductors are provided for conveying signals between the groups. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.
Control profile
Bahram Ahanin from Beverly Hills, CA, age ~70 Get Report