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Ashwin Raghunathan Phones & Addresses

  • Burlingame, CA
  • Pleasanton, CA
  • Fremont, CA
  • San Mateo, CA
  • San Francisco, CA
  • Daly City, CA
  • Atlanta, GA

Resumes

Resumes

Ashwin Raghunathan Photo 1

Architect

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Location:
1075 Rollins Rd, Burlingame, CA 94010
Industry:
Computer Games
Work:
Zynga - San Francisco since Jul 2010
Senior Software Engineer

Zynga Inc since Jul 2010
Senior Software Engineer

RemeBUDDY Jan 2012 - Oct 2012
Founder, Architect and Developer, RemeBuddy

Project Cloudburst Jan 2010 - May 2010
Developer

Tata Consultancy Services Jan 2008 - May 2008
Front End Developer/ Intern
Education:
Georgia Institute of Technology 2008 - 2010
MS, Computer Science
PSG College of Technology 2004 - 2008
BE, Computer Science
Georgia Institute of Technology
Master's degree, Atlanta (Computer Science
PSG College of Technology
Bachelor of Engineering, degree, Computer Science
Skills:
Java
Python
Jquery
C++
Shell Scripting
Data Structures
Algorithms
Web Services
C
Javascript
Unix
Databases
Software Engineering
Sql
Git
Opengl
Object Oriented Design
Php
Mysql
Rest
Apache
Css
Html
Web Applications
Perl
Puppet
Nagios
Munin
Graphite
Languages:
Tamil
English
Ashwin Raghunathan Photo 2

Tech Lead As Contractor At Apple

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Position:
Technology Lead at Infosys
Location:
San Francisco Bay Area
Industry:
Information Technology and Services
Work:
Infosys - Cupertino since Jun 2012
Technology Lead

Infosys Jun 2006 - Jul 2012
Technology Analyst
Education:
SSNCE 2002 - 2006
BTech, Information Technology
Skills:
PL/SQL
Spring
Web Services
Oracle
Servlets
XML
Unix
Microsoft SQL Server
Requirements Analysis
Requirements Gathering
SDLC
SQL
Business Objects

Publications

Us Patents

Techniques For Minimizing Control Voltage Ripple Due To Charge Pump Leakage In Phase Locked Loop Circuits

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US Patent:
7932757, Apr 26, 2011
Filed:
Feb 9, 2009
Appl. No.:
12/367969
Inventors:
Ashwin Raghunathan - Santa Clara CA, US
Marzio Pedrali-Noy - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
H03L 7/06
US Classification:
327158, 327149
Abstract:
Techniques for adaptively control of a loop filter sampling interval to mitigate the effects of charge pump leakage current in an apparatus including a phase lock loop circuit are provided. In one aspect, the apparatus includes a voltage controlled oscillator (VCO), a phase frequency detector (PFD) providing a phase comparison operation, a loop filter providing a control voltage to lock the VCO to a desired operating frequency, and a charge pump configured to provide an output signal to the loop filter in response to at least one of an UP pulse and a DOWN pulse. The apparatus further includes a sampling switch, coupled between an input of the loop filter, an output of the charge pump, and characterized by a sampling interval. A sampling switch controller is configured to adaptively control the width of the sampling interval in order to mitigate the effects of leakage current from the charge pump by closing the sampling switch in advance of the phase comparison operation and opening the sampling switch when the phase comparison operation is completed.

Supply-Regulated Phase-Locked Loop (Pll) And Method Of Using

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US Patent:
7973612, Jul 5, 2011
Filed:
Apr 26, 2009
Appl. No.:
12/430104
Inventors:
Ashwin Raghunathan - Santa Clara CA, US
Marzio Pedrali-Noy - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
H03L 7/099
US Classification:
331186, 331185, 331 34, 331 74
Abstract:
A supply-regulated Phase-locked loop (PLL) is provided. The PLL comprises a supply-regulating loop, a voltage-controlled oscillator (VCO), and a programmable decoupling capacitor array for the VCO. The capacitance of the VCO decoupling capacitor array is adjustable to be equal to N times C, where N is the current value of a multiplication factor of a divide-by-N circuit and Cis a unit capacitance characterized for a processing technology chosen for fabricating the decoupling capacitor array. When the PLL switches from one frequency band to another, a higher-order pole introduced by the VCO decoupling capacitor tracks the PLL reference frequency, thus improving the PLL operational stability.

Recalibration Systems And Techniques For Electronic Memory Applications

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US Patent:
8159888, Apr 17, 2012
Filed:
Mar 1, 2010
Appl. No.:
12/714767
Inventors:
Ashwin Raghunathan - Santa Clara CA, US
Marzio Pedrali-Noy - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G11C 7/00
US Classification:
365193, 365194
Abstract:
A memory circuit includes a delay module receiving a strobe signal and producing a delayed strobe signal therefrom. The memory circuit also includes a calibration module that initiates recalibration of the delay module when the calibration module discerns that the delayed strobe signal is within a predetermined proximity of an edge of a reference signal. The memory circuit can be included in a memory interface. Furthermore, in some embodiments, a strobe signal can be used as the reference signal.

Techniques For Minimizing Control Voltage Noise Due To Charge Pump Leakage In Phase Locked Loop Circuits

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US Patent:
8164369, Apr 24, 2012
Filed:
Feb 9, 2009
Appl. No.:
12/367980
Inventors:
Ashwin Raghunathan - Santa Clara CA, US
Marzio Pedrali-Noy - San Diego CA, US
Assignee:
Qualcomm Incorporated - San Diego CA
International Classification:
H03L 7/06
US Classification:
327158, 327149
Abstract:
Techniques for adaptively control of a loop filter sampling interval to mitigate the effects of charge pump output noise in an apparatus including a phase lock loop circuit are provided. In one aspect, the apparatus includes a voltage controlled oscillator (VCO), a phase frequency detector (PFD) providing a phase comparison operation, a loop filter providing a control voltage to lock the VCO to a desired operating frequency, and a charge pump configured to provide an output signal to the loop filter in response to at least one of an UP pulse and a DOWN pulse. The apparatus further includes a sampling switch, coupled between an input of the loop filter, an output of the charge pump, and characterized by a sampling interval. A sampling switch controller is configured to adaptively control the width of the sampling interval in order to mitigate the effects of output noise from the charge pump by closing the sampling switch in advance of the phase comparison operation and opening the sampling switch when the phase comparison operation is completed.

Pll Charge Pump With Reduced Coupling To Bias Nodes

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US Patent:
8330511, Dec 11, 2012
Filed:
Apr 20, 2010
Appl. No.:
12/763418
Inventors:
Ashwin Raghunathan - Santa Clara CA, US
Sameer Wadhwa - San Diego CA, US
Marzio Pedrali-Noy - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
H03L 7/06
US Classification:
327158, 327149, 327150, 327159
Abstract:
A charge pump includes an UP current mirror and a DN current mirror. The UP current mirror is controlled by an input UP signal and supplies charge onto an output node. The DN current mirror is controlled by an input DN signal and draws charge from the output node. The input UP and DN signals may be received from a phase detector in a Phase-Locked Loop (PLL). To prevent disturbances on bias nodes of the UP and DN current mirrors that otherwise might occur, replica circuits of portions of the UP and DN current mirrors are provided. Each replica circuit is coupled to a bias node of a corresponding current mirror, but is controlled by an input signal of opposite polarity to the input signal that controls the current mirror so that the replica circuit creates disturbances that tend to counteract disturbances created by switching of the current mirror.

Supply-Regulated Vco Architecture

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US Patent:
8362848, Jan 29, 2013
Filed:
Apr 7, 2011
Appl. No.:
13/082313
Inventors:
Ashwin Raghunathan - Santa Clara CA, US
Marzio Pedrali-Noy - San Diego CA, US
Sameer Wadhwa - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
H03L 1/00
H03L 7/099
H03K 3/03
US Classification:
331186, 331 34, 331 50, 331 57, 327156, 327158
Abstract:
A supply-regulated VCO exhibits reduced or no supply sensitivity peaking. The VCO includes an oscillator whose supply current is regulated to control the oscillating frequency of the oscillator. A VCO input signal controls the supply current so that there is a relationship between the input signal and the oscillator output frequency. Power supply noise that might otherwise affect oscillator operation is shunted from a supply current input lead of the oscillator to ground by a bypass capacitor. In one example, an auxiliary circuit supplies an auxiliary supply current to the oscillator, thereby reducing the amount of supply current a supply regulation control loop circuit must supply. In another example, a supply regulation control loop circuit supplies a control current to a main oscillator, but the bypass capacitor is not coupled to this oscillator but rather is coupled to a slave oscillator that is injection locked to the main oscillator.

Delay Line That Tracks Setup Time Of A Latching Element Over Pvt

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US Patent:
8363485, Jan 29, 2013
Filed:
Sep 15, 2009
Appl. No.:
12/559585
Inventors:
Ashwin Raghunathan - Santa Clara CA, US
Marzio Pedrali Noy - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G11C 7/10
G11C 7/22
US Classification:
36518905, 36518915, 365193, 365194, 3652331, 36523313
Abstract:
A latching element latches incoming data into an integrated circuit. The latching element (for example, a latch or flip-flop) can be considered to include a data path portion, a clock path portion, and an ideal latching element. In one embodiment, an open-loop replica of the data path portion is disposed in a clock signal path between a clock input terminal of the integrated circuit and a clock input lead of the latching element. In a second embodiment, an additional replica of the clock path portion is disposed in a data signal path between a data terminal of the integrated circuit and a data input lead of the latching element. The replica circuits help prevent changes in skew between a data path propagation time to the ideal latching element and clock path propagation time to the ideal latching element. Setup times remain substantially constant over PVT (process, supply voltage, temperature).

Periodic Timing Jiperiodic Timing Jitter Reduction In Oscillatory Systems

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US Patent:
20100194471, Aug 5, 2010
Filed:
Apr 29, 2009
Appl. No.:
12/432515
Inventors:
Ashwin Raghunathan - Santa Clara CA, US
Marzio Pedrali-Noy - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
H03B 25/00
G06F 1/04
US Classification:
327596, 713600
Abstract:
A device including a voltage regulator with an adaptive switching frequency circuit for noise-sensitive analog circuits, such as oscillatory systems with phase-lock loops (PLLs) and voltage-controlled oscillators (VCOs) is described. In an exemplary embodiment, the device includes a reference clock oscillator, a low-jitter oscillator, a power supply including a clock signal input to regulate a power supply voltage for the low-jitter oscillator, a clock detector to generate a clock detector control signal when the low-jitter oscillator output frequency is stable, and a multiplexer to select between a reference clock oscillator output signal and a low-jitter oscillator output signal as the clock signal input to the power supply to mitigate effects of period jitter in the low-jitter oscillator output signal when the clock detector control signal is asserted. In a further exemplary embodiment, a clock detector control signal is configured to control the multiplexer to select the low-jitter oscillator output signal as the clock signal input to the power supply when the low-jitter oscillator output frequency is stable.
Ashwin Raghunathan from Burlingame, CA, age ~39 Get Report