Search

Arun K Somani

from Ames, IA
Age ~73

Arun Somani Phones & Addresses

  • 2445 Ridgetop Cir, Ames, IA 50014 (515) 268-9718
  • 16609 126Th Ave, Woodinville, WA 98072 (425) 487-3065 (515) 268-9718
  • Seattle, WA
  • Hillsborough, CA
  • Webster City, IA
  • Bryn Mawr, PA
  • Pittsburgh, PA
  • 2445 Ridgetop Cir, Ames, IA 50014 (515) 290-1339

Work

Position: Homemaker

Education

Degree: High school graduate or higher

Emails

a***i@rcn.com

Professional Records

Medicine Doctors

Arun Somani Photo 1

Arun K. Somani

View page
Specialties:
Psychiatry
Work:
Arun K Somani MD
9700 Stirling Rd STE 104, Hollywood, FL 33024
(954) 433-2533 (phone), (954) 433-5575 (fax)
Education:
Medical School
Sawai Man Singh Med Coll, Rajasthan Univ, Jaipur, Rajasthan, India
Graduated: 1983
Procedures:
Psychiatric Diagnosis or Evaluation
Psychiatric Therapeutic Procedures
Conditions:
Bipolar Disorder
Depressive Disorders
Post Traumatic Stress Disorder (PTSD)
Anxiety Dissociative and Somatoform Disorders
Anxiety Phobic Disorders
Languages:
English
Spanish
Description:
Dr. Somani graduated from the Sawai Man Singh Med Coll, Rajasthan Univ, Jaipur, Rajasthan, India in 1983. He works in Hollywood, FL and specializes in Psychiatry.
Arun Somani Photo 2

Arun Kumar Somani

View page
Specialties:
Psychiatry
Education:
S M S Medical College (1982) Psychiatry

Resumes

Resumes

Arun Somani Photo 3

Associate Dean For Research, College Of Engineering

View page
Location:
Des Moines, IA
Industry:
Higher Education
Work:
Iowa State University
Associate Dean For Research, College of Engineering

Iowa State University May 2003 - Sep 2010
Professor and Chair

Iowa State University May 2003 - Sep 2010
Anson Marston Distinguished Professor

Ieee May 2003 - Sep 2010
Fellow of

University of Washington Sep 1985 - Aug 1997
Professor of Elect Engineer and Comp Sci and Engineer
Education:
Mcgill University 1982 - 1985
Doctorates, Doctor of Philosophy, Computer Engineering
Indian Institute of Technology, Delhi 1976 - 1979
Birla Institute of Technology and Science, Pilani 1968 - 1973
Skills:
Algorithms
C
Analysis
Interests:
Civil Rights and Social Action
Education
Science and Technology
Human Rights
Arts and Culture
Arun Somani Photo 4

Distinguished Professor

View page
Location:
Ames, IA
Industry:
Higher Education
Work:
Iowa State University
Distinguished Professor
Skills:
Des
Acis
Luxembourg

Business Records

Name / Title
Company / Classification
Phones & Addresses
Arun Somani
Chairman
Iowa State University of Science and Technology
University
2215 Coover Hall, Ames, IA 50011
(515) 294-2663

Publications

Isbn (Books And Publications)

Survivability And Traffic Grooming In WDM Optical Networks

View page
Author

Arun Somani

ISBN #

0521853885

1999 8th International Conference on Computer Communications and Networks: Proceedings 11-13 October 1999, Boston, Massachusetts

View page
Author

Arun Somani

ISBN #

0780357949

The 5th International Conference on Advanced Computing: Proceedings December 15-17, 1997, Hotel Park Sheraton, TTK Road, Chennai (Madras)

View page
Author

Arun K. Somani

ISBN #

0074630199

Opticomm 2003: Optical Networking and Communications

View page
Author

Arun K. Somani

ISBN #

0819451800

Us Patents

Location Information Recovery And Management For Mobile Networks

View page
US Patent:
6718173, Apr 6, 2004
Filed:
Sep 30, 1999
Appl. No.:
09/409130
Inventors:
Arun K. Somani - Ames IA
Govindarajan Krishnamurthy - North Billerica MA
Assignee:
Iowa State University Research Foundation - Ames IA
International Classification:
H04Q 720
US Classification:
4554561, 455432, 455435, 455433, 455445, 370331, 370338, 370407, 707200
Abstract:
Systems and methods for recovering and managing location information in mobile communication networks using a fast recovery protocol and load balanced query and update processes. According to the fast recovery protocol, if a location update processor does not receive a message from a global database server acknowledging receipt by the global database server of a location update message after a predetermined retry interval has elapsed since the location update message was sent by the location update processor, the location update processor sends a location update retry message after each predetermined retry interval elapses until the location update processor receives an acknowledgement message from the global database server. The global database server can use the location update retry messages and the predetermined retry interval to recover from a database or link failure. The recovery period using the fast recovery protocol is bounded by the predetermined retry interval.

Location Information Recovery And Management For Mobile Networks

View page
US Patent:
7113795, Sep 26, 2006
Filed:
Jan 30, 2004
Appl. No.:
10/769456
Inventors:
Arun K. Somani - Ames IA, US
Govindarajan Krishnamurthi - North Billerica MA, US
Assignee:
University of Iowa Research Foundation, Inc. - Ames IA
International Classification:
H04Q 7/20
US Classification:
4554561, 707201, 707 10, 4554142, 709205, 709217
Abstract:
Systems and methods for recovering and managing location information in mobile communication networks using a fast recovery protocol and load balanced query and update processes. According to the fast recovery protocol, if a location update processor does not receive a message from a global database server acknowledging receipt by the global database server of a location update message after a predetermined retry interval has elapsed since the location update message was sent by the location update processor, the location update processor sends a location update retry message after each predetermined retry interval elapses until the location update processor receives an acknowledgement message from the global database server. The global database server can use the location update retry messages and the predetermined retry interval to recover from a database or link failure. The recovery period using the fast recovery protocol is bounded by the predetermined retry interval.

Real Time Music Recognition And Display System

View page
US Patent:
7323629, Jan 29, 2008
Filed:
Jul 16, 2003
Appl. No.:
10/622083
Inventors:
Arun Somani - Ames IA, US
Wu Tao - Ames IA, US
Raed Adhami - Ames IA, US
Liang Zhao - College Park MD, US
Anil Sahai - Webster City IA, US
International Classification:
G10H 1/00
US Classification:
84470R, 84475, 84477 R, 700 94
Abstract:
Systems and methods for performing simple and quick real time single music note recognition algorithm based on fuzzy pattern matching are disclosed. In one aspect, the systems and methods use a 256-point FFT and fuzzy pattern identification and recognition method. The systems and methods can recognize a note as short as 0. 125 seconds in a frequency range from 16 Hz to 4000 Hz, with 11. 025 KHz sampling rate and 8-bit per sampling signal. The systems and methods may be used as part of a music tutor system that receives a played note, identifies the played note, and compares the played note with a reference note. An indication may be given as to whether the played note matched the reference note.

Access Mechanisms For Efficient Sharing In A Network

View page
US Patent:
7536477, May 19, 2009
Filed:
Feb 23, 2004
Appl. No.:
10/784568
Inventors:
Srinivasan Ramasubramanian - Tucson AZ, US
Arun K. Somani - Ames IA, US
Assignee:
Iowa State University Research Foundation, Inc. - Ames IA
International Classification:
G06F 15/173
US Classification:
709238, 455517, 370503, 370224
Abstract:
One embodiment provides a computer-implemented method for processing data on a node. In this embodiment, the node first determines if a first transit buffer on the node is empty, wherein the first transit buffer is capable of holding one or more data packets destined for another node. If the first transit buffer is empty, the node transmits in a first direction a data packet stored in a first local buffer, wherein the first local buffer is capable of holding one or more data packets originating from the node. If, however, the first transit buffer is not empty, the node transmits in the first direction one or more data packets stored in the first transit buffer if a first transmission condition is satisfied. If the first transmission condition is not satisfied, the node transmits in the first direction a data packet stored in the first local buffer.

Superscale Processor Performance Enhancement Through Reliable Dynamic Clock Frequency Tuning

View page
US Patent:
7671627, Mar 2, 2010
Filed:
Apr 22, 2008
Appl. No.:
12/107415
Inventors:
Arun Somani - Ames IA, US
Mikel Bezdek - West Des Moines IA, US
Assignee:
Iowa State University Research Foundation, Inc. - Ames IA
International Classification:
H03K 19/173
US Classification:
326 46, 326 93, 714724
Abstract:
In the case of a pipelined processor, a performance gain is achievable through dynamically generating a main clock signal associated with a synchronous logic circuit and generating at least one backup register clock signal, the backup register clock signal at the same frequency as the main clock signal and phase shifted from the main clock signal to thereby provide additional time for one or more of the logic stages to execute. Error detection or error recovery may be performed using the backup registers. The methodology can further be extended, to design a system with cheaper technology and simple design tools that initially operates at slower speed, and then dynamically overclocks itself to achieve improved performance, while guaranteeing reliable execution.

Logic Element Architecture For Generic Logic Chains In Programmable Devices

View page
US Patent:
8438522, May 7, 2013
Filed:
Sep 24, 2008
Appl. No.:
12/237076
Inventors:
Michael T. Frederick - Colorado Springs CO, US
Arun K. Somani - Ames IA, US
Assignee:
Iowa State University Research Foundation, Inc. - Ames IA
International Classification:
G06F 17/50
US Classification:
716117, 716121, 716128
Abstract:
A reconfigurable device includes an arrangement of a plurality of cells and routing resources for transmitting signals between the cells. The plurality of cells comprises carry-select reuse cells, each of the carry-select reuse cells configured to provide for performing non-arithmetic operations using a reuse arithmetic carry chain interconnecting adjacent cells.

Dynamic Advance Reservation With Delayed Allocation

View page
US Patent:
20120327953, Dec 27, 2012
Filed:
Jun 26, 2012
Appl. No.:
13/533355
Inventors:
Vinod Mandayam VOKKARANE - Waltham MA, US
Arun Kumar SOMANI - Ames IA, US
Assignee:
Iowa State University Research Foundation, Inc. - Ames IA
University of Massachusetts - Boston MA
International Classification:
H04B 7/212
US Classification:
370442
Abstract:
A method of scheduling data transmissions from a source to a destination, includes the steps of: providing a communication system having a number of channels and a number of paths, each of the channels having a plurality of designated time slots; receiving two or more data transmission requests; provisioning the transmission of the data; receiving data corresponding to at least one of the two or more data transmission requests; waiting until an earliest requested start time T; allocating at the current time each of the two or more data transmission requests; transmitting the data; and repeating the steps of waiting, allocating, and transmitting until each of the two or more data transmission requests that have been provisioned for a transmission of data is satisfied. A system to perform the method of scheduling data transmissions is also described.

Multiprocessor System With Write Generate Method For Updating Cache

View page
US Patent:
55242120, Jun 4, 1996
Filed:
Apr 27, 1992
Appl. No.:
7/876775
Inventors:
Arun K. Somani - Woodinville WA
Craig M. Wittenbrink - Seattle WA
Chung-Ho Chen - Seattle WA
Robert E. Johnson - Seattle WA
Kenneth H. Cooper - Marysville WA
Robert M. Haralick - Seattle WA
Assignee:
University of Washington - Seattle WA
International Classification:
G06F 15167
G06F 1517
US Classification:
39520008
Abstract:
A plurality of program processors, shared memory, dual port memory, external cache memory and a control processor form a multiprocessor system. A shared memory bus links the program processors, shared memory, dual port memory and external cache memory. Program processor I/O occurs through a pair of serial I/O channels coupled to one port of the dual port memory. A write generate mode is implemented for updating cache by first allocating lines of shared memory as write before read areas. For such lines, cache tags are updated directly on cache misses without reading from memory. A hit is forced for such line, resulting in valid data at the updated part and invalid data at the remaining portion. Thus, part of the line is written to and the rest invalidated. The invalid portions are not read, unless preceded by a write operation.
Arun K Somani from Ames, IA, age ~73 Get Report