Resumes
Resumes
Argos Cue Phones & Addresses
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Kalamazoo, MI
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2101 Burton Dr, Austin, TX 78741
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6307 Bluff Springs Rd, Austin, TX 78744 (512) 440-7528
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Lafayette, IN
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W Lafayette, IN
Publications
Us Patents
Ccd Imager Analog Processor Systems And Methods
View pageUS Patent:
7286176, Oct 23, 2007
Filed:
Apr 8, 2004
Appl. No.:
10/820577
Inventors:
Douglas R. Holberg - Wimberley TX, US
Sandra M. Johnson - Buda TX, US
Nadi R. Itani - Austin TX, US
Argos R. Cue - Austin TX, US
Sandra M. Johnson - Buda TX, US
Nadi R. Itani - Austin TX, US
Argos R. Cue - Austin TX, US
Assignee:
Cirrus Logic, Inc. - Austin TX
International Classification:
H04N 5/222
H04N 5/228
H03M 1/12
H03M 1/38
H04N 5/228
H03M 1/12
H03M 1/38
US Classification:
34833301, 3482221, 348572, 341161
Abstract:
A processing system for a charge coupled device (CCD) or CMOS imaging system includes a multi-mode, multiple current level, correlated double sample and variable gain (CDS/VGA) circuit for receiving data from a CCD system, subject to horizontal and vertical timing signals for the system which are locally generated by the processing system itself. The processing system particularly includes programmable timing circuitry for controlling the detection of pixel intensity values from elements of a two-dimensional pixel array, with a programmable low-frequency master vertical timing circuit driving a high-frequency horizontal timing circuit, wherein the vertical and horizontal timing signals are independently locally provided to the array from the analog processor actually sampling the array. The architecture of the processing system further includes a correlated double sampler, a black level clamp, and an A/D conversion module. The processing system includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA) having amplifiers of selectable current level to enable reduced data resolution, an analog-to-digital converter (ADC) having a selectable bit-width output and coupled to said VGA circuit, and a gain circuit coupled to said ADC.
Ccd Imager Analog Processor Systems And Methods
View pageUS Patent:
6720999, Apr 13, 2004
Filed:
Mar 31, 1999
Appl. No.:
09/283112
Inventors:
Douglas R. Holberg - Wimberley TX
Sandra M. Johnson - Buda TX
Nadi R. Itani - Austin TX
Argos R. Cue - Austin TX
Sandra M. Johnson - Buda TX
Nadi R. Itani - Austin TX
Argos R. Cue - Austin TX
Assignee:
Cirrus Logic, Inc. - Austin TX
International Classification:
H04N 5228
US Classification:
3482221, 3482291, 348241, 348250, 348257, 333 14
Abstract:
A processing system for a charge coupled device (CCD) or CMOS imaging system includes a multi-mode, multiple current level, correlated double sample and variable gain (CDS/VGA) circuit for receiving data from a CCD system, subject to horizontal and vertical timing signals for the system which are locally generated by the processing system itself. The processing system particularly includes programmable timing circuitry for controlling the detection of pixel intensity values from elements of a two-dimensional pixel array, with a programable low-frequency master vertical timing circuit driving a high-frequency horizontal timing circuit, wherein the vertical and horizontal timing signals are independently locally provided to the array from the analog processor actually sampling the array. The architecture of the processing system further includes a correlated double sampler, a black level clamp, and an A/D conversion module. The processing system includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA) having amplifiers of selectable current level to enable reduced data resolution, an analog-to-digital converter (ADC) having a selectable bit-width output and coupled to said VGA circuit, and a gain circuit coupled to said ADC.