Resumes
Resumes
Product Integration Manager- Silicon Photonics Product Development
View pageLocation:
440 Cesano Ct, Palo Alto, CA 94306
Industry:
Semiconductors
Work:
Intel Corporation - Santa Clara, CA since Feb 2012
Fab Capital Equipment Development Engineer
Intel Corporation - Santa Clara, CA Sep 2011 - Feb 2012
Senior Technical Consultant, Intel new business development
Intel Corporation - Chandler, AZ Nov 2005 - Aug 2011
Group Lead/Process TD Engineer, Assembly Technology Development
Hutchinson Technology Inc Sep 2004 - Oct 2005
Process development engineer
Philips Nat lab Research Center Jan 2004 - May 2004
Graduate Intern
Fab Capital Equipment Development Engineer
Intel Corporation - Santa Clara, CA Sep 2011 - Feb 2012
Senior Technical Consultant, Intel new business development
Intel Corporation - Chandler, AZ Nov 2005 - Aug 2011
Group Lead/Process TD Engineer, Assembly Technology Development
Hutchinson Technology Inc Sep 2004 - Oct 2005
Process development engineer
Philips Nat lab Research Center Jan 2004 - May 2004
Graduate Intern
Education:
University of Texas 2002 - 2004
M. S, Materials Science and Engineering University of Madras 1998 - 2002
Bachelor of Engineering (Honors), Chemical Engineering
M. S, Materials Science and Engineering University of Madras 1998 - 2002
Bachelor of Engineering (Honors), Chemical Engineering
Skills:
Manufacturing
Design of Experiments
Failure Analysis
Semiconductors
Process Simulation
R&D
Materials
Start Ups
Spc
Process Engineering
Engineering
Research and Development
Thin Films
Characterization
Electronics Packaging
Jmp
Cross Functional Team Leadership
Statistical Process Control
Design of Experiments
Failure Analysis
Semiconductors
Process Simulation
R&D
Materials
Start Ups
Spc
Process Engineering
Engineering
Research and Development
Thin Films
Characterization
Electronics Packaging
Jmp
Cross Functional Team Leadership
Statistical Process Control
Languages:
English
Archana Ashok
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