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Anthony L Tsangaropoulos

from Redwood City, CA
Age ~56
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Also known as:
Anthony Lycourgos Tsangaropoulos, Anthon Tsangaropoulos, Anthony S, Anthony L, Anthony O, Lonnie Goldman
Phone and address:
1535 Hess Rd APT 1, Redwood City, CA 94061
(650) 591-5393
Related to:
Theodoros M Daskalakis, 53Sondra Goldman, 87Jason N Remmerde, 53Robert Remmerde, 78Melissa Yaich, 51Roy Goldman, 58
Connected to:
George C Tsangarides, 62Maria I Tsangari, 57Maria E Tsangaroulis, 38Paris A Tsangaris, 38Stacy A Tsangaris, 48Laura Tsangeos, 63Bree A Tsaniff, 45Alex Tsao, 62Allison Tsao, 29Andrea Tsao, 32

Anthony Tsangaropoulos Phones & Addresses

  • 1535 Hess Rd APT 1, Redwood City, CA 94061 (650) 591-5393
  • 321 Clifton Ave, San Carlos, CA 94070 (650) 591-5393
  • 621 Magnolia Dr, San Mateo, CA 94402 (650) 571-5393
  • Foster City, CA
  • Belmont, CA
  • 321 Clifton Ave, San Carlos, CA 94070

Work

Position: Professional/Technical

Education

Degree: Graduate or professional degree

Skills

IC • Product Development • WiFi • DVB • Systems Engineering • RF

Industries

Wireless

Resumes

Resumes

Anthony Tsangaropoulos Photo 1

Anthony Tsangaropoulos

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Location:
San Francisco Bay Area
Industry:
Wireless
Skills:
IC
Product Development
WiFi
DVB
Systems Engineering
RF

Publications

Us Patents

Direct Digital Synthesizer For Reference Frequency Generation

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US Patent:
8242850, Aug 14, 2012
Filed:
May 21, 2010
Appl. No.:
12/800808
Inventors:
Anthony L. Tsangaropoulos - San Carlos CA, US
David Francois Guillou - Pittsburgh PA, US
Assignee:
Resonance Semiconductor Corporation - Pittsburgh PA
International Classification:
H03B 1/00
H03K 21/00
H03K 21/08
H03K 21/38
US Classification:
331 74, 327115, 377 48
Abstract:
A direct digital frequency synthesizer having a multi-modulus divider, a numerically controlled oscillator and a programmable delay generator. The multi-modulus divider receives an input clock having an input pulse frequency fand outputs some integer fraction of those pulses at an instantaneous frequency fthat is some integer fraction (1/P) of the input frequency. The multi-modulus divider selects between at least two ratios of P (1/P or 1/P+1) in response to a signal from the numerically controlled oscillator. The numerically controlled oscillator receives an accumulator increment (i. e. , the number of divided pulse edges) required before an overflow occurs that causes the multi-modulus divider to change divider ratios in response to an overflow. The numerically controlled oscillator also outputs both the overflow signal and a delay signal to the delay generator. The delay signal contains phase-dithering noise that is induced by input from a pseudo-random noise generator.

Direct Digital Synthesizer For Reference Frequency Generation

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US Patent:
20100052797, Mar 4, 2010
Filed:
Aug 28, 2008
Appl. No.:
12/229948
Inventors:
L. Richard Carley - Sewickley PA, US
Anthony L. Tsangaropoulos - San Carlos CA, US
Esa Tarvainen - Graz, AT
Assignee:
Renaissance Wireless Corporation - Pittsburgh PA
International Classification:
H03L 7/00
US Classification:
331 18
Abstract:
A direct digital frequency synthesizer having a multi-modulus divider, a numerically controlled oscillator and a programmable delay generator. The multi-modulus divider receives an input clock having an input pulse frequency fand outputs some integer fraction of those pulses at an instantaneous frequency fthat is some integer fraction (1/P) of the input frequency. The multi-modulus divider selects between at least two ratios of P(1/P or 1/P+1) in response to a signal from the numerically controlled oscillator. The numerically controlled oscillator receives a value which is the accumulator increment (i.e. the number of divided pulse edges) required before an overflow occurs that causes the multi-modulus divider to change divider ratios in response to receiving an overflow signal. The numerically controlled oscillator also outputs both the overflow signal and a delay signal to the delay generator that further controls the frequency of the multi-modulus divider output signal (V) to provide an output signal (V) with an fthat has improved phase and timing jitter performance over prior art direct digital frequency synthesizer architectures.

Direct Digital Synthesizer For Reference Frequency Generation

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US Patent:
20130021069, Jan 24, 2013
Filed:
Jul 31, 2012
Appl. No.:
13/562512
Inventors:
Anthony L. Tsangaropoulos - San Carlos CA, US
David Francois Guillou - Pittsburgh PA, US
Assignee:
Cymatics Laboratories Corp. - Pittsburgh PA
International Classification:
H03K 21/00
US Classification:
327115
Abstract:
A direct digital frequency synthesizer includes a multi-modulus divider, a numerically controlled oscillator and a programmable delay generator. The divider receives an input clock having an input pulse frequency and outputs some integer fraction of those pulses at an instantaneous frequency that is some integer fraction (1/P) of the input frequency. The divider selects between at least two ratios of P (1/P or 1/P+1) in response to a signal from the oscillator. The oscillator receives a value which is the accumulator increment (i.e. the number of divided pulse edges) required before an overflow occurs that causes the divider to change divider ratios in response to receiving an overflow signal. The oscillator also outputs both the overflow signal and a delay signal to the delay generator. The delay signal contains phase-dithering noise that is induced by input into the accumulator of an increment generated from a pseudo-random noise generator.

Time Slotted Scan Receiver

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US Patent:
20210120496, Apr 22, 2021
Filed:
Aug 31, 2018
Appl. No.:
15/733329
Inventors:
- Santa Clara CA, US
Chen Meng - Sunnyvale CA, US
Yuwei Zhang - Pleasanton CA, US
Jinyong Lee - Fremont CA, US
Oren Kaidar - Binyamina, IL
Sharon Heruti - Petah Tikva, IL
Thomas W. Brown - Portland OR, US
Assaf Gurevitz - Ramat Hasharon, IL
Anthony Tsangaropoulos - San Carlos CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04W 52/02
H04B 17/318
H04B 17/345
H04W 56/00
H04L 1/00
Abstract:
In one embodiment, an apparatus of a wireless communication device includes control circuitry to cause receiver circuitry of the wireless communication device to switch between an on-mode and an off-mode. The apparatus also includes synchronizing circuitry to: perform a correlation on signals of a packet received by the receiver circuitry when in the on-mode to detect a pattern in the received signals, and cause the control circuitry to hold the receiver circuitry in the on-mode based on detection of the pattern in the received signals. The apparatus further includes demodulation circuitry to process additional signals of the packet received by the receiver circuitry when held in the on-mode.

Arrangement For Concurrent Detection Of Signals In A Receiver

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US Patent:
20180063873, Mar 1, 2018
Filed:
Aug 31, 2016
Appl. No.:
15/252707
Inventors:
- Santa Clara CA, US
Anthony Tsangaropoulos - San Carlos CA, US
International Classification:
H04W 76/02
H04L 5/00
H04L 12/24
Abstract:
An arrangement for detection of multiple signals concurrently is disclosed. The arrangement includes a demodulator component, a mixer and a detector. The demodulator component is configured to demodulate or obtain one or more components from a received signal. The mixer is configured to mix the one or more components into a folded signal using a plurality of varied local oscillator (LO) signals. The detector is configured to identify a valid signal within the folded signal and to initiate a response for the identified valid signal.

Devices And Methods For Transmit Concurrency By Conditioned Signal Combining

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US Patent:
20160381641, Dec 29, 2016
Filed:
Jun 26, 2015
Appl. No.:
14/752103
Inventors:
Itzik Shahar - Kadima, IL
Anthony Tsangaropoulos - San Carlos CA, US
Ilan Sutskover - Hadera, IL
Brian Sublett - Menlo Park CA, US
Dongsheng Bi - Fremont CA, US
Ronen Kronfeld - Shoham, IL
International Classification:
H04W 52/04
H04W 4/00
Abstract:
Embodiments pertain to systems, methods, and component devices for Tx-Tx transmit concurrency by combining signals before power amplification. One example embodiment includes validity check circuitry configured to check a transmission power for a Bluetooth signal against a first threshold transmission power, a Bluetooth Power Amplifier, and a WLAN power amplifier. A switching network controlled by the validity check circuitry and configured to couple the Bluetooth input to Bluetooth power amplifier input when the transmission power for the Bluetooth signal is above the first threshold transmission power and to couple the Bluetooth signal with a WLAN signal for input to the shared WLAN power amplifier when the transmission power for the Bluetooth signal is less than the first threshold transmission power.

Preemptive Automatic Gain Control (Agc) For Interference Mitigation

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US Patent:
20160381647, Dec 29, 2016
Filed:
Jun 29, 2015
Appl. No.:
14/753529
Inventors:
- Santa Clara CA, US
Reuven Lavie - Hertzelia, IL
Brian J. Sublett - Menlo Park CA, US
Anthony Tsangaropoulos - San Carlos CA, US
Jinyong Lee - Fremont CA, US
Dongsheng Bi - Fremont CA, US
Dor Chay - Tel-Aviv, IL
International Classification:
H04W 52/52
H04W 24/08
H04W 4/00
Abstract:
Described herein are technologies related to an implementation of interference mitigation in a receiver of a portable device. A preemptive-automatic gain control (AGC) system mitigates a collocated or external interfering signal in a receiver of a portable device. The receiver of the portable device receives and processes a data packet of a first radio frequency (RF) signal that includes a Bluetooth (BT) signal, a Wi-Fi signal, a near field communications (NFC), 3G, 4G, or the like. During the processing of the data packet, a collocated or an external second RF signal is detected and received by the receiver. The second RF signal includes an interfering Bluetooth (BT) uplink transmission, a near field communications (NFC) transmission signal, a Wi-Fi transmission signal, 3G or 4G uplink transmission, an LTE signal, or the like.
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Anthony L Tsangaropoulos from Redwood City, CA, age ~56 Get Report