Anthony P Ingraham

6414509, Jul 2, 2002

May 3, 2000

09/564652

Anilkumar Chinuprasad Bhatt - Johnson City NY
Leo Raymond Buda - Vestal NY
Robert Douglas Edwards - Binghamton NY
Paul Joseph Hart - Endicott NY
Anthony Paul Ingraham - Endicott NY
Voya Rista Markovich - Endwell NY
Jaynal Abedin Molla - Endicott NY
Richard Gerald Murphy - Binghamton NY
George Frederick Walker - New York NY
Bette Jaye Whalen - Vestal NY
Richard Stuart Zarr - Apalachin NY

International Business Machines Corporation - Armonk NY

G01R 3102

324765, 324760, 324754

A method of testing semiconductor chips is disclosed. The individual semiconductor chips have I/O, power, and ground contacts. In the method of the invention a chip carrier is provided. The chip carrier has contacts corresponding to the contacts on the semiconductor chip. The carrier contacts have dendritic surfaces. The chip contacts are brought into conductive contact with the conductor pads on the chip carrier. Test signal input vectors are applied to the inputs of the semiconductor chip, and output signal vectors are recovered from the semiconductor chip. After testing, the chip may be removed from the substrate. Alternatively, the chip may be bonded through the dendritic conductor pads to the substrate after successful testing.

59536233, Sep 14, 1999

Apr 10, 1997

8/835690

Christina M. Boyko - Endicott NY
Anthony P. Ingraham - Endicott NY
Voya R. Markovich - Endwell NY
David J. Russell - Apalachin NY

International Business Machines Corporation - Armonk NY

H01L 2144

438612

A solder interconnection uses preferably lead-rich balls for making a low temperature chip attachment directly to any of the higher levels of packaging substrate. After a solder ball has been formed using standard processes, a ball limiting metal mask is formed using photoresist. A thin cap layer of preferably pure tin is deposited on a surface of the solder balls using a tin aqueous immersion process.

51374617, Aug 11, 1992

Oct 30, 1990

7/606007

Perminder S. Bindra - South Salem NY
Jerome J. Cuomo - Lincolndale NY
Thomas P. Gall - Endwell NY
Anthony P. Ingraham - Endicott NY
Sung K. Kang - Chappaqua NY
Paul Lauro - Pomona NY
David N. Light - Friendsville PA
Voya R. Markovich - Endwell NY
Ekkehard F. Miersch - Schoenaich, DE
Jaynal A. Molla - Endicott NY
Douglas O. Powell - Endicott NY
John J. Ritsko - Mount Kisco NY
George J. Saxenmeyer - Apalachin NY
Jack A. Varcoe - Endwell NY
George F. Walker - New York NY

International Business Machines Corporation - Armonk NJ

H01R 909

439 74

A separable and reconnectable connection for electrical equipment is provided that is suitable for miniaturization in which vertical interdigitating members integrally attached and protruding from a planar portion are accommodated in control of damage in lateral displacement that occurs on mating with an opposite similar contact. Displacement damage is averted through accommodating lateral stresses by providing one or more of a conformal opposing contact, by strengthening through coating and base reinforcement and a deformable coating. The contacts are fabricated by physical and chemical processes including sputtering, normal and pulse electroplating and chemical vapor deposition. The contacts on completion are provided with a surrounding immobilizing material that enhances rigidity.

56729804, Sep 30, 1997

Feb 15, 1996

8/602167

Richard Gordon Charlton - Essex Junction VT
George Charles Correia - Essex Junction VT
Mark Andrew Couture - Milton VT
Gary Ray Hill - Jericho VT
Kibby Barth Horsford - Charlotte VT
Anthony Paul Ingraham - Endicott NY
Michael David Lowell - Endicott NY
Voya Rista Markovich - Endwell NY
Gordon Charles Osborne - Essex Junction VT
Mark Vincent Pierson - Binghamton NY

International Business Machines Corporation - Armonk NY

G01R 1073
G01R 3128

324755

A method and apparatus for testing semi-conductor chips is disclosed. The individual semiconductor chips have I/O contacts. The apparatus is provided with an interposer that has contacts corresponding to the contacts on the semiconductor chip. Both the chip and the interposer contacts can be any known type including metal ball, bumps, or tabs or may be provided with dendritic surfaces. The chip contacts are first brought into relative loose temporary contact with the contacts on the interposer and then a compressive force greater that 5 grams per chip contact is applied to the chip to force the chip contacts into good electrical contact with the interposer contacts. Testing of the chip is then performed. The tests may include heating of the chip as well as the application of signals to the chip contacts. After testing the chip is removed from the substrate.

59949104, Nov 30, 1999

Sep 24, 1998

9/160057

Francis Joseph Downes - Vestal NY
Anthony Paul Ingraham - Endicott NY
Jaynal Abedin Molla - Endicott NY

International Business Machines Corporation - Armonk NY

G01R 1073
G01R 3102

324757

An apparatus, and a corresponding method, for stress-testing wire bond-type semiconductor chips is disclosed. The apparatus includes a clamp housing, with a spring-loaded screw extending through the top end of the housing. Contained within the clamp housing is a substantially rigid, electrically insulating base plate positioned at a lower end of the clamp housing. The upper surface of the base plate includes a depression which contains an insert fabricated either from an elastomeric material or a semiconductor material, such as silicon. A flexible, electrically insulating layer made from, for example, polyimide, overlies the base plate and insert. Significantly, the upper surface of the flexible, electrically insulating layer includes a plurality of dendritic contacts. It is through these dendritic contacts that electrical contact is made to the contact pads of a wire bond-type semiconductor chip.

59263695, Jul 20, 1999

Jan 22, 1998

9/009862

Anthony P. Ingraham - Endicott NY
Glenn L. Kehley - Endicott NY
Sanjeev B. Sathe - Johnson City NY
John R. Slack - Vestal NY

International Business Machines Corporation - Armonk NY

H05K 720

361699

A multi-chip carrier which uses less lateral mounting space on the surface of a circuit board or card can be formed using flexible circuitized material. Lateral space is compressed by utilizing more vertical space to package chips and components. The problem of cooling multiple chips in a tight space may be accomplished by integrating the heat sink in with the circuit carrier and having the heat sink double as a support structure. A flex material is folded or shaped. Different regions of the flex are used for mounting chips, mounting support mechanisms, or mounting the structure on a carrier or substrate.

59492465, Sep 7, 1999

Jan 28, 1997

8/789926

Jerome A. Frankeny - Taylor NY
Anthony P. Ingraham - Endicott NY
James Steven Kamperman - Endicott NY
James Robert Wilcox - Vestal NY

International Business Machines - Armonk NY

G01R 3126

324765

A technique for testing/stressing integrated circuit devices, especially wafers, having a plurality of contacts on one face thereof arranged in a predetermined pattern is provided. An interposer having a dielectric substrate and a device contact face and a tester contact face is provided. A first plurality of releasable connectors on the device contact are face arranged in the same predetermined pattern, and a second plurality of releasable connectors are arranged in the same predetermined pattern on the tester contact face. The releasable connections are formed of dendrites. Conducting vias connect the corresponding connectors of the first and second releasable connectors respectively. A test head is provided having a plurality of contact pads also arranged in the same predetermined pattern. Circuitry is provided on the test head to connect each of the contact pads thereon with external leads extending to provide signal contact to each of the contact pads on the test head.

53915143, Feb 21, 1995

Apr 19, 1994

8/229883

Thomas P. Gall - Endwell NY
Anthony P. Ingraham - Endicott NY

International Business Machines Corporation - Armonk NY

H01L 2128
H01L 2158
H01L 2160

437183

A method of flip chip bonding an integrated circuit chip to a chip carrier. A high melting temperature composition, such as a binary Pb/Sn alloy, is deposited on contacts on, for example, the chip, and constituents of a low melting composition, such as Bi and Sn, are codeposited on contacts on, for example, the chip carrier. The chip and chip carrier are then heated. This causes the lower melting temperature composition, for example the Bi and Sn, to melt and form a low melting temperature alloy, such as a Bi/Sn alloy. The low melting alloy dissolves the higher melting composition, as Pb/Sn. This results in the formation of a solder bond of a low melting point third composition, such as a ternary alloy of Bi/Pb/Sn.