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Anish Muttreja Phones & Addresses

  • Pittsford, NY
  • Denver, CO
  • San Diego, CA
  • Woburn, MA
  • Wakefield, MA
  • San Jose, CA
  • Patchogue, NY
  • Santa Clara, CA
  • 10860 Ivy Hill Dr UNIT 8, San Diego, CA 92131

Work

Company: Qualcomm Mar 2013 Address: Greater San Diego Area Position: Senior engineer

Education

Degree: Masters School / High School: Princeton University 2002 to 2004 Specialities: Electrical Engineering

Skills

Perl • Asic • Microprocessors • Algorithms • Simulations • Python • Rtl Design • Soc • Software Development • Debugging • Vlsi • C • Fpga • Data Analysis • Verilog • Application Specific Integrated Circuits • Very Large Scale Integration • Power Aware Chip Design • Hardware • Simulation • C++

Languages

Hindi

Interests

Children • Economic Empowerment • Civil Rights and Social Action • Politics • Education • Environment • Poverty Alleviation • Science and Technology • Disaster and Humanitarian Relief

Industries

Semiconductors

Resumes

Resumes

Anish Muttreja Photo 1

Senior Staff Engineer

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Location:
San Diego, CA
Industry:
Semiconductors
Work:
Qualcomm - Greater San Diego Area since Mar 2013
Senior Engineer

NVIDIA since Aug 2007
Senior ASIC Design Engineer

NEC Laboratories America Jun 2006 - Sep 2006
Intern

Telcordia Technologies Jun 2005 - Aug 2005
Research Intern
Education:
Princeton University 2002 - 2004
Masters, Electrical Engineering
Indian Institute of Technology, Kharagpur 1998 - 2002
Bachelor or Technology, 2002
Delhi Public School, Noida
Skills:
Perl
Asic
Microprocessors
Algorithms
Simulations
Python
Rtl Design
Soc
Software Development
Debugging
Vlsi
C
Fpga
Data Analysis
Verilog
Application Specific Integrated Circuits
Very Large Scale Integration
Power Aware Chip Design
Hardware
Simulation
C++
Interests:
Children
Economic Empowerment
Civil Rights and Social Action
Politics
Education
Environment
Poverty Alleviation
Science and Technology
Disaster and Humanitarian Relief
Languages:
Hindi

Publications

Us Patents

Methods And Apparatuses For Extended Current Limit For Power Regulation

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US Patent:
20210294369, Sep 23, 2021
Filed:
Mar 19, 2021
Appl. No.:
17/207478
Inventors:
- San Diego CA, US
Edgar Marti-Arbona - Chandler AZ, US
Gordon Lee - Gilbert AZ, US
Anish Muttreja - Denver CO, US
Ravi Jenkal - San Diego CA, US
International Classification:
G05F 1/573
G05F 1/56
Abstract:
A method and apparatuses for power regulation using an extended current limit are disclosed. The power regulator detects an occurrence of an output current of the regulator exceeding a first current limit, triggers an extended current limit timer based on the detected occurrence, regulates the output current according to a second current limit higher than the first current limit based on a duration of the extended current limit timer, and regulates the output current according to the first current limit based on an expiration of the duration of the extended current limit timer.

Processor Load Step Balancing

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US Patent:
20190332138, Oct 31, 2019
Filed:
Apr 30, 2018
Appl. No.:
15/967456
Inventors:
- San Diego CA, US
Anish Muttreja - Denver CO, US
Ravi Jenkal - San Diego CA, US
International Classification:
G06F 1/12
G06F 1/06
Abstract:
A system is provided that controls the clocking of a processor depending upon its usage of execution units. As the processor transitions from a default mode of operation using a default number of the execution units to an increased load mode of operation using an increased number of the execution units, a current drawn by the processor from a power rail remains substantially unchanged.

Flexible And Scalable Energy Model For Estimating Energy Consumption

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US Patent:
20170199558, Jul 13, 2017
Filed:
Aug 16, 2016
Appl. No.:
15/238267
Inventors:
- San Diego CA, US
Anish Muttreja - San Diego CA, US
Eduardus Antonius Metz - Unionville, CA
Lucille Garwood Sylvester - Boulder CO, US
Brian Salsbery - Superior CO, US
International Classification:
G06F 1/32
Abstract:
At least one processor may determine, for each of a plurality of operating performance points (OPPs) that each comprise a memory frequency and a graphics processing unit (GPU) frequency, an estimated energy consumption associated with a memory and the GPU operating at the respective memory frequency and GPU frequency to process a workload based at least in part on a plurality of energy equations associated with the plurality of OPPs. The at least one processor may set the memory and the GPU to operate at the respective memory frequency and GPU frequency of one of the plurality of OPPs to process the workload based at least in part on the estimated energy consumption.
Anish X Muttreja from Pittsford, NY, age ~44 Get Report