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Anirban Rahut

from Saratoga, CA
Age ~48
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Also known as:
Anirban Hut, Rahut Anirban, Null Null, N T
Connected to:
Ajay K Rai, 61Akriti Rai, 37Amarendra K Rai, 71Amrinder S Rai, 48Amrita Rai, 59Anam Z Rai, 35Anand D Rai, 45Anju Rai, 28Anupam Rai, 52Aren S Rai, 37

Anirban Rahut Phones & Addresses

  • Saratoga, CA
  • 1990 Garzoni Pl, Santa Clara, CA 95054 (408) 969-0249
  • 825 Evelyn Ave, Sunnyvale, CA 94086 (408) 720-9766
  • 1180 Lochinvar Ave, Sunnyvale, CA 94087 (408) 244-5084
  • 1125 Delna Manor Ln, San Jose, CA 95128
  • Lovettsville, VA
  • 1770 Jeffrey Ct, Santa Clara, CA 95051 (408) 969-0249

Work

Company: Facebook May 2016 Position: Engineering

Education

Degree: Masters, Master of Science In Electrical Engineering School / High School: Stanford University 2002 to 2006 Specialities: Electronics Engineering, Electronics

Skills

Distributed Systems • Big Data • C++ • Elasticsearch • Mongodb • Iot • Algorithms • Mysql • Python • Scalability • Operating Systems • Machine Learning • Eda • Fpga • Semiconductors • Hadoop • Linux • Engineering Management • Hbase • Software Engineering • Databases

Languages

English

Ranks

Certificate: Oracle Mysql Certification

Industries

Computer Software

Resumes

Resumes

Anirban Rahut Photo 1

Engineering

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Location:
12877 Glen Brae Dr, Saratoga, CA 95070
Industry:
Computer Software
Work:
Facebook
Engineering
Splunk Jan 2013 - Jun 2015
Principal Engineer
Xilinx Dec 2000 - Apr 2012
Principal Engineer and Manager
Xilinx Dec 2000 - Jun 2008
Engineering and Management Positions
Microsoft Jun 2000 - Dec 2000
Sde and T
Education:
Stanford University 2002 - 2006
Masters, Master of Science In Electrical Engineering, Electronics Engineering, Electronics Indian Institute of Technology, Kanpur 1994 - 1998
Bachelors, Bachelor of Technology, Computer Science Ispat English Medium School
Skills:
Distributed Systems
Big Data
C++
Elasticsearch
Mongodb
Iot
Algorithms
Mysql
Python
Scalability
Operating Systems
Machine Learning
Eda
Fpga
Semiconductors
Hadoop
Linux
Engineering Management
Hbase
Software Engineering
Databases
Languages:
English
Certifications:
Oracle Mysql Certification
Oracle

Publications

Us Patents

Method And Apparatus For Selecting Programmable Interconnects To Reduce Clock Skew

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US Patent:
6952813, Oct 4, 2005
Filed:
Jul 30, 2003
Appl. No.:
10/631564
Inventors:
Anirban Rahut - San Jose CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F017/50
US Classification:
716 6, 716 5
Abstract:
A method and apparatus for selecting programmable interconnects to reduce clock skew is described. A routing tree for clock signals is created having routes and clock pin nodes. Delays of the clock signals to the clock pin nodes are determined. The routing tree is balanced to a target clock skew, such as zero clock skew, for the clock signals provided to the clock pin nodes. Programmable interconnect circuits are selectively added to reduce clock skews of the clock signals, where the clock skews being reduced at the clock pin nodes are for at least a portion of the clock pin nodes. Additionally described are determining clock propagation delays to clock pins and balancing a clock tree using computer aided design.

Upper-Bound Calculation For Placed Circuit Design Performance

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US Patent:
7051312, May 23, 2006
Filed:
Jun 24, 2003
Appl. No.:
10/603219
Inventors:
Anirban Rahut - San Jose CA, US
Sudip K. Nag - San Jose CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 13, 716 12, 716 14
Abstract:
Within a computer automated tool, a method () of estimating an upper-bound of an operational frequency of at least a portion of a placed circuit design can include identifying () a clock source within the placed circuit design, wherein the clock source is associated with a clock domain, and determining () an initial routing of the clock domain. The method also can include determining () a minimum path slack corresponding to each connection of the clock domain. Connections of the clock domain which have a lowest minimum path slack can be marked (). One or more marked connections which are not routed in delay mode can be identified and routed in delay mode () allowing sharing of routing resources by different nets.

Using Router Feedback For Placement Improvements For Logic Design

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US Patent:
7076758, Jul 11, 2006
Filed:
Aug 7, 2003
Appl. No.:
10/637242
Inventors:
Sankaranarayanan Srinivasan - Longmont CO, US
Anirban Rahut - San Jose CA, US
Krishnan Anandh - San Jose CA, US
Sudip K. Nag - San Jose CA, US
Assignee:
XILINX, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 11, 716 6, 716 10, 716 13
Abstract:
Within a computer automated tool, a method of physical circuit design can include assigning initial locations to components in the circuit design and determining an initial routing of connections between components in the circuit design using an overlap mode. The method also can include determining timing critical connections and selectively relocating components with at least one timing critical connection prior to performing a detailed routing of the circuit design.

Method And Apparatus For Facilitating Signal Routing Within A Programmable Logic Device

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US Patent:
7306977, Dec 11, 2007
Filed:
Aug 29, 2003
Appl. No.:
10/651808
Inventors:
Vinay Verma - Cupertino CA, US
Anirban Rahut - San Jose CA, US
Sudip K. Nag - San Jose CA, US
Jason H. Anderson - Toronto, CA
Rajeev Jayaraman - Saratoga CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H01L 21/82
US Classification:
438129, 257E21575, 438599, 716 13
Abstract:
Method and apparatus for facilitating signal routing within a programmable logic device having routing resources is described. In an example, the routing resources are formed into groups where, for each of the groups, the routing resources are of a same type. Pairs of the groups are related by an association of at least one routing resource in one group of a pair of groups capable of being electrically connected to at least one other routing resource in another group of the pair of groups.

Run-Time Efficient Methods For Routing Large Multi-Fanout Nets

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US Patent:
7376926, May 20, 2008
Filed:
Apr 29, 2005
Appl. No.:
11/119012
Inventors:
Raymond Kong - San Francisco CA, US
Anirban Rahut - Sunnyvale CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 12, 716 13, 716 14
Abstract:
A method of limiting the routing resources of an integrated circuit (IC) that are available for use when routing multi-fanout nets can include selecting a multi-fanout net comprising a source and a plurality of loads and identifying each region of the IC which does not include at least one of the plurality of loads. Each of the regions can have a defined geometry. A type of routing resource can be selected which has a physical orientation with respect to the IC that corresponds to the geometry of the regions of the IC. Each routing resource of the selected type that is located within a region of the IC which does not include at least one of the plurality of loads can be excluded from consideration when routing the multi-fanout net.

Methods Of Routing Low-Power Designs In Programmable Logic Devices Having Heterogeneous Routing Architectures

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US Patent:
7389485, Jun 17, 2008
Filed:
Mar 28, 2006
Appl. No.:
11/390925
Inventors:
Anirban Rahut - Sunnyvale CA, US
Satyaki Das - Los Gatos CA, US
Arifur Rahman - San Jose CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 12, 716 5, 716 6, 716 13, 716 14, 716 15
Abstract:
Methods of routing user designs in programmable logic devices (PLDs) having heterogeneous routing structures, i. e. , PLDs including both high-power and low-power interconnect resources. A first pass routing step is performance-based, e. g. , utilizes a cost function biased towards the high-power interconnect resources. The first routed design is then evaluated to identify non-critical nets in the first routed design that can yield the most power-saving benefit by being retargeted to the low-power interconnect resources. For example, a sorted list of nets can be created in which the identified nets are evaluated based on the capacitance per load pin of each net. A second pass routing step is then performed, e. g. , rerouting the nets identified as being non-critical and having the greatest potential power-saving benefit. In some embodiments, the permitted increase in the delay of each rerouted net is bound by the slack of the net as routed in the first routed design.

Assigning Inputs Of Look-Up Tables To Improve A Design Implementation In A Programmable Logic Device

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US Patent:
7424697, Sep 9, 2008
Filed:
Feb 16, 2007
Appl. No.:
11/707317
Inventors:
Hasan Arslan - Santa Clara CA, US
Anirban Rahut - Sunnyvale CA, US
Assignee:
XILINX, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 16, 716 10
Abstract:
Methods for improving an implementation of a design in a programmable logic device (PLD). A topological level of the design implementation is determined for each look-up table (LUT) of the PLD. A subset of the LUTs that are on the critical timing paths of the design implementation is determined. For each LUT in the subset at each topological level, a set combinations is determined for assigning signals to the inputs of the LUT. A current assignment of the signals to the LUT inputs is initialized according to the design implementation. For each LUT in the subset at each topological level, the method determines whether a respective assignment for each combination in the set for the LUT improves a timing metric for the LUT relative to the current assignment for the LUT, and the current assignment is updated when the respective assignment improves the timing metric for the LUT.

Method And Apparatus For Selecting Programmable Interconnects To Reduce Clock Skew

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US Patent:
7430728, Sep 30, 2008
Filed:
Aug 10, 2005
Appl. No.:
11/200686
Inventors:
Anirban Rahut - Sunnyvale CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 6, 716 5
Abstract:
A method and apparatus for selecting programmable interconnects to reduce clock skew is described. A routing tree for clock signals is created having routes and clock pin nodes. Delays of the clock signals to the clock pin nodes are determined. The routing tree is balanced to a target clock skew, such as zero clock skew, for the clock signals provided to the clock pin nodes. Programmable interconnect circuits are selectively added to reduce clock skews of the clock signals, where the clock skews being reduced at the clock pin nodes are for at least a portion of the clock pin nodes. Additionally described are determining clock propagation delays to clock pins and balancing a clock tree using computer aided design.
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Anirban Rahut from Saratoga, CA, age ~48 Get Report