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Aninda K Roy

from Portland, OR
Age ~54
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Also known as:
Roy Kumar Aninda, Roy K Aninda, Roy Anenda
Phone and address:
13556 Payne Dr, Portland, OR 97229
(503) 533-4970
Related to:
Arup K Roy, 58
Connected to:
Abinash C Roy, 68Ajay K Roy, 46Ajit K Roy, 73Alan F Roy, 62Albert Roy, 49Alfredo Roy, 89Alissa Roy, 46Allie E Roy, 35Alma R Roy, 59Amita A Roy, 59

Aninda Roy Phones & Addresses

  • 13556 Payne Dr, Portland, OR 97229 (503) 533-4970 (503) 412-8894
  • 12753 NW Millford St, Portland, OR 97229
  • Beaverton, OR
  • 410 River Side Ct, Santa Clara, CA 95054 (408) 980-9197
  • 867 Winchester Blvd, San Jose, CA 95128 (408) 261-8318

Resumes

Resumes

Aninda Roy Photo 1

Director Product Management

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Location:
19750 northwest Phillips Rd, Hillsboro, OR 97124
Industry:
Semiconductors
Work:
Intel Corporation
Director Product Management
Sun Microsystems 1999 - 2003
Senior Member of Technical Staff
Intel Corporation 1999 - 2003
Engineering Manager and Principal Engineer
Rockwell Automation/Allen Bradley 1996 - 1999
Computer Analyst
Education:
Indian Institute of Technology
University of Wisconsin - Madison
Masters, Electronics Engineering, Electronics Indian Institute of Technology, Kharagpur
Bachelors
Skills:
Integration
Engineering Management
Networking
Software Development
Application Specific Integrated Circuits
System on A Chip
Aninda Roy Photo 2

Aninda Roy

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Publications

Us Patents

Marginable Clock-Derived Reference Voltage Method And Apparatus

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US Patent:
6658061, Dec 2, 2003
Filed:
Dec 19, 2001
Appl. No.:
10/027812
Inventors:
Aninda Roy - San Jose CA
Assignee:
Sun Microsystems, Inc. - Palo Alto CA
International Classification:
H04B 300
US Classification:
375257, 375260, 455 69
Abstract:
A method for receiving data from a sending system in a receiving system includes receiving a pair of differential clock signals from the sending system, determining a reference voltage in the receiving system in response to the pair of differential clock signals, receiving a test data signal from the sending system, adjusting the reference voltage to form an updated reference voltage in response to the test data signal, receiving a single-ended data signal from the sending system relative to a reference voltage and determining a data signal in response to the single-ended data signal and to the updated reference voltage.

Delay Variability Reduction Method And Apparatus

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US Patent:
6664850, Dec 16, 2003
Filed:
Dec 19, 2001
Appl. No.:
10/027799
Inventors:
Aninda Roy - San Jose CA
Assignee:
Sun Microsystems, Inc. - Palo Alto CA
International Classification:
H03F 102
US Classification:
330 9, 330 69, 330280, 341118, 341120, 341143, 341144, 341155
Abstract:
A method for reducing delay variability in a differential receiver includes receiving a plurality of differential input signals, determining a first transition delay time of an output in response to the plurality of differential input signals, determining a second transition delay time of the output in response to the plurality of differential input signals, and modifying capacitance coupled to the output in response to the first transition delay time and to the second transition delay time.

Self-Biased Driver Amplifiers For High-Speed Signaling Interfaces

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US Patent:
6756824, Jun 29, 2004
Filed:
Nov 12, 2002
Appl. No.:
10/292261
Inventors:
Aninda K. Roy - San Jose CA
Samudyatha Suryanarayana - Sunnyvale CA
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
H03B 100
US Classification:
327108, 327112, 327 51, 327379, 327170
Abstract:
Disclosed are novel methods and apparatus for efficiently providing self-biased driver amplifiers for high-speed signaling interfaces. In an embodiment of the present invention, a self-biased amplifier driver is disclosed. The driver includes a sensing circuit to sense a presence of noise in a power supply signal. The sensing circuit may include a current source to adjust an output signal of the sensing circuit in accordance with the power supply noise. The driver may further include: an amplifier coupled to the sensing circuit to amplify the sensing circuit output signal, a pre-driver to receive a data signal, and a driver coupled to the amplifier and the pre-driver to receive an amplifier output signal and a pre-driver output signal.

High-Resolution Single-Ended Source-Synchronous Receiver

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US Patent:
6762623, Jul 13, 2004
Filed:
Dec 16, 2002
Appl. No.:
10/320148
Inventors:
Samudyatha Suryanarayana - Sunnyvale CA
Aninda K. Roy - San Jose CA
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
H03K 19082
US Classification:
326105, 326 98, 326113, 327 68, 327292
Abstract:
Disclosed are novel methods and apparatus for efficiently providing high-resolution single-ended source synchronous receivers. In an embodiment of the present invention, a source-synchronous receiver is disclosed. The receiver includes: a first amplifier to receive a clock signal and a data signal, the first amplifier providing a first output signal; a second amplifier to receive a complementary clock signal and the data signal, the second amplifier providing a second output signal; a third amplifier to receive the clock signal and the data signal, the third amplifier providing a third output signal, the second and third output signals being combined to provide a fifth output; and a fourth amplifier to receive the complementary clock signal and the data signal, the fourth amplifier providing a fourth output signal, the first and fourth output signals being combined to provide a sixth output signal.

I/O Power Supply Resonance Compensation Technique

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US Patent:
6781355, Aug 24, 2004
Filed:
Oct 18, 2002
Appl. No.:
10/274165
Inventors:
Claude R. Gauthier - Cupertino CA
Aninda K. Roy - San Jose CA
Brian W. Amick - Austin TX
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G05F 1652
US Classification:
323233
Abstract:
An apparatus for compensating for the effects of resonance in an integrated circuits power distribution network is provided. A resonance detector monitors transmissions from the integrated circuit for certain bit patterns that may excite the power distribution network at a specific frequency and cause power supply resonance. Power supply resonance causes an increase in power supply impedance. When offending transmissions are detected, the resonance detector activates a damping element on the integrated circuit which dampens the resonance. The damping element is a resistive device between two power supply lines that decreases power supply impedance when activated.

Unity Gain Interpolator For Delay Locked Loops

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US Patent:
6788123, Sep 7, 2004
Filed:
Jan 8, 2003
Appl. No.:
10/338224
Inventors:
Aninda K. Roy - San Jose CA
Assignee:
n Microsystems, Inc. - Santa Clara CA
International Classification:
H03K 312
US Classification:
327261, 327561, 330130
Abstract:
A method and apparatus for delaying a clock signal involves a first clock path arranged to propagate a first clock signal; a second clock path arranged to propagate a second clock signal; and an interpolator arranged as a unity gain operational amplifier. An amount of delay between the first and second clock signals is determined by a control voltage potential.

Source Synchronous Interface Using Variable Digital Data Delay Lines

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US Patent:
6791360, Sep 14, 2004
Filed:
Sep 11, 2002
Appl. No.:
10/241202
Inventors:
Claude R. Gauthier - Cupertino CA
Brian W. Amick - Austin TX
Aninda Roy - San Jose CA
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
H03K 1900
US Classification:
326 93, 326 96, 327149
Abstract:
A source synchronous interface determines an amount of delay for an incoming data signal and a phase offset for a latch device that latches the incoming data signal. A delay locked loop may be a dual loop delay locked loop, in which case, the loops may use a low jitter, local clock signal and an input clock signal that was transmitted with the data signal. The low jitter, local clock signal may provide a stable source from which to derive good clock signal edge transitions. The input clock signal may be used to determine the long term clock signal drift. A finite state machine within the dual loop delay locked loop may provide the necessary information for the amount of delay and the phase offset. The delay of the incoming data signal is produced by a digital delay line.

Design-For-Test Technique For A Delay Locked Loop

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US Patent:
6815986, Nov 9, 2004
Filed:
Jul 16, 2002
Appl. No.:
10/196622
Inventors:
Aninda Roy - San Jose CA
Claude Gauthier - Fremont CA
Brian Amick - Austin TX
Dean Liu - Sunyvale CA
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
H03L 706
US Classification:
327149, 327158, 324 7653, 324 7654
Abstract:
A delay locked loop implementing design-for-test features to test for, among other, stuck-at-faults is provided. The delay locked loop uses multiplexers as design-for-test devices for controllability purposes and flip-flops as design-for-test devices for observability purposes. Such implementation of design-for-test features within a delay locked loop allows for pre-packaging delay locked loop verification and testing.
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Aninda K Roy from Portland, OR, age ~54 Get Report