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Anil C Kota

from Alvin, TX
Age ~45
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Also known as:
Anil Chowdary Kota, Anil Chowdary Lota, Anil Koda, Anil Kotta
Related to:
Sri Sesha Chandrika Kota
Connected to:
Ajay K Kota, 65Henneh B Kota, 35Margaret H Kota, 72Matt Kota, 44Naganjan P Kota, 67Pavan K Kota, 45Prasanna K Kota, 54Rahul Kota, 31Ramesh Kota, 49Sahiti Kota, 46

Anil Kota Phones & Addresses

  • Alvin, TX
  • Apex, NC
  • 6927 Westleigh Pl, San Diego, CA 92126 (858) 231-0107
  • 10482 Hollingsworth Way #185, San Diego, CA 92127
  • Clemson, SC

Publications

Us Patents

Method And Apparatus For Testing One Time Programmable (Otp) Arrays

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US Patent:
20130188410, Jul 25, 2013
Filed:
Mar 15, 2012
Appl. No.:
13/420832
Inventors:
Gregory A. Uvieghara - San Diego CA, US
Amer Christophe G. Cassier - San Diego CA, US
Anil C. Kota - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G11C 29/00
G11C 17/00
US Classification:
365 94, 365201
Abstract:
An array of one time programmable (OTP) devices includes a first set of pre-configurable memory devices appended to one or more columns of me array and a second set of pre-configurable memory devices appended to one or more rows of the array. The pre-configurable memory devices may be additional OTP devices or read only memory (ROM) devices that can be configured to store a predetermined test pattern for the array. Rows, columns and functionalities of the array can be tested based on the stored test pattern. OTP devices in the array may then be programmed after successful testing based on the test pattern stored.

Circuits Configured To Remain In A Non-Program State During A Power-Down Event

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US Patent:
20130294139, Nov 7, 2013
Filed:
May 7, 2012
Appl. No.:
13/465132
Inventors:
Esin Terzioglu - San Diego CA, US
Gregory A. Uvieghara - San Diego CA, US
Mehdi H. Sani - San Diego CA, US
Anil Kota - San Diego CA, US
Sei Seung Yoon - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G11C 17/00
G06F 17/50
US Classification:
365 94, 716100
Abstract:
In a particular embodiment, an apparatus includes a one-time programmable (OTP) memory circuit configured to be responsive to a programming voltage. The OTP memory circuit includes an OTP memory array including OTP memory cells, a first power switch configured to decouple the OTP memory array from the programming voltage, and a second power switch configured to decouple a subset of the OTP memory cells from the programming voltage.

Memory With A Sense Amplifier Isolation Scheme For Enhancing Memory Read Bandwidth

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US Patent:
20230087277, Mar 23, 2023
Filed:
Sep 22, 2021
Appl. No.:
17/481601
Inventors:
- San Diego CA, US
Anil Chowdary KOTA - San Diego CA, US
Dhvani SHETH - San Diego CA, US
Chulmin JUNG - San Diego CA, US
International Classification:
G11C 11/419
G11C 11/412
Abstract:
A memory is provided that includes a self-timed memory circuit that controls the isolation of a sense amplifier from a column selected by a column multiplexer until the completion of a bit line voltage difference development delay. The self-timed memory circuit also controls the release of a pre-charge for the sense amplifier responsive to the completion of the bit line voltage difference development delay.

Memory With Reduced Capacitance At A Sense Amplifier

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US Patent:
20230066241, Mar 2, 2023
Filed:
Aug 27, 2021
Appl. No.:
17/446195
Inventors:
- San Diego CA, US
Anil Chowdary KOTA - San Diego CA, US
Hochul LEE - Los Angeles CA, US
International Classification:
G11C 11/419
H03K 19/20
Abstract:
A memory is provided that includes multiple memory banks, each one of the memory banks being associated with a read multiplexer. A first read multiplexer couples a first plurality of bit lines to a first sense node pair, and a second read multiplexer couples a second plurality of bit lines to a second sense node pair. A first sense amplifier is coupled to the first sense node pair. The second sense node pair may be coupled to the same sense amplifier or a different sense amplifier.

Systems And Methods To Provide Write Termination For One Time Programmable Memory Cells

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US Patent:
20210280263, Sep 9, 2021
Filed:
Mar 6, 2020
Appl. No.:
16/811145
Inventors:
- San Diego CA, US
Anil Chowdary KOTA - San Diego CA, US
Keejong KIM - Phoenix AZ, US
International Classification:
G11C 17/18
G11C 17/16
Abstract:
A One Time Programmable (OTP) memory, includes: a first driver coupled to a reference cell by a first bit line; a second driver coupled to an OTP cell by a second bit line; and a comparator having a first input coupled to the first bit line and the reference cell, a second input coupled to the second bit line and the OTP cell, and an output coupled to a logic circuit configured to control the first driver and the second driver.

Fuse-Based Logic Repair

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US Patent:
20200394274, Dec 17, 2020
Filed:
Jun 14, 2019
Appl. No.:
16/442347
Inventors:
- San Diego CA, US
Anil Chowdary KOTA - San Diego CA, US
Fadoua CHAFIK - San Diego CA, US
International Classification:
G06F 17/50
Abstract:
A method for repairing logic design includes inserting primary logic gates in a primary logic design path of a logic chip. The method also includes inserting alternative logic gates in an alternate logic design path of the logic chip. The alternate logic design path and the primary logic design path are coupled to multiple fuses. The potentially defective design is repaired by selecting between the alternate logic design path and the primary logic design path with the fuses when the logic design is defective.

Physically Unclonable Function (Puf) In Programmable Read-Only Memory (Prom)

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US Patent:
20200365222, Nov 19, 2020
Filed:
May 14, 2019
Appl. No.:
16/411316
Inventors:
- San Diego CA, US
Keejong KIM - Phoenix AZ, US
Anil Chowdary KOTA - San Diego CA, US
Chulmin JUNG - San Diego CA, US
International Classification:
G11C 17/18
G11C 17/16
G06F 1/06
H04L 9/32
Abstract:
Certain aspects of the present disclosure provide apparatus and techniques for random bit generation. One example apparatus generally includes a switch, a fuse coupled to the switch, a driver circuit having an output coupled to the fuse, an amplifier having an input coupled to the driver circuit, and a counter coupled to an output of the amplifier.

N-Well Switching Circuit

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US Patent:
20140369152, Dec 18, 2014
Filed:
Aug 29, 2014
Appl. No.:
14/472953
Inventors:
- San Diego CA, US
Gregory Ameriada Uvieghara - Murrieta CA, US
Sei Seung Yoon - San Diego CA, US
Balachander Ganesan - Mountain View CA, US
Anil Chowdary Kota - San Diego CA, US
International Classification:
H03K 17/22
H03K 17/687
G11C 8/08
US Classification:
36523006, 327537
Abstract:
A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit biases the switched n-well to prevent voltage damage to the dual-mode PMOS transistor despite its relatively small size and thin gate-oxide thickness.
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Anil C Kota from Alvin, TX, age ~45 Get Report