Search

Ananthan Ayyasamy

from Portland, OR
Age ~48
Get Report
Also known as:
Ananth Ayyasamy, Ananthan Ayasamy, Ananthan Ananthan Ayyasamy, Ayasamy Ananthan
Phone and address:
4081 NW Lois Elaine Ter, Portland, OR 97229
Connected to:
Saravanan Ayyasamy, 44Ahmad K Ayyash, 46Ahmads Ayyash, 61Angela Ayyash, 32Eddie E Ayyash, 64Hasan A Ayyash, 91Linda M Ayyash, 46Nadia A Ayyash, 38Sami Ayyat, 57Ahmet Ayyildiz, 74

Ananthan Ayyasamy Phones & Addresses

  • 4081 NW Lois Elaine Ter, Portland, OR 97229
  • Hillsboro, OR
  • 1517 W Swan Pl, Chandler, AZ 85286
  • Maricopa, AZ
  • 16676 NW Desert Canyon Dr, Beaverton, OR 97006

Work

Company: Intel Aug 2000 Position: Engineering manager

Education

Degree: MBA School / High School: Arizona State University, W. P. Carey School of Business 2008 to 2010

Skills

Soc • Asic • Systemverilog • Rtl Design • Debugging • Sdlc • Vlsi • Phy • Unix • Static Timing Analysis • Logic Synthesis • Clocking • Place and Route • Emulation • Silicon Validation • 10G Ethernet • Lan Switching • Pcie • Project Management • Engineering Management • Contract Management • Vendor Management • Theory of Constraints • Scrum • Cross Functional Team Leadership • Embedded Systems • Very Large Scale Integration • Application Specific Integrated Circuits • System on A Chip

Industries

Semiconductors

Resumes

Resumes

Ananthan Ayyasamy Photo 1

Senior Strategic Planner

View page
Location:
16676 northwest Desert Canyon Dr, Beaverton, OR 97006
Industry:
Semiconductors
Work:
Intel since Aug 2000
Engineering Manager
C-DoT Aug 1997 - Aug 2000
Research Engineer
Education:
Arizona State University, W. P. Carey School of Business 2008 - 2010
MBA National Institute of Technology Tiruchirappalli 1993 - 1997
BE, ECE
Skills:
Soc
Asic
Systemverilog
Rtl Design
Debugging
Sdlc
Vlsi
Phy
Unix
Static Timing Analysis
Logic Synthesis
Clocking
Place and Route
Emulation
Silicon Validation
10G Ethernet
Lan Switching
Pcie
Project Management
Engineering Management
Contract Management
Vendor Management
Theory of Constraints
Scrum
Cross Functional Team Leadership
Embedded Systems
Very Large Scale Integration
Application Specific Integrated Circuits
System on A Chip

Publications

Us Patents

Multichip Package Link

View page
US Patent:
20200320031, Oct 8, 2020
Filed:
Jan 31, 2020
Appl. No.:
16/779377
Inventors:
- Santa Clara CA, US
Mahesh Wagh - Portland OR, US
Debendra Das Sharma - Saratoga CA, US
Gerald S. Pasdast - San Jose CA, US
Ananthan Ayyasamy - Beaverton OR, US
Xiaobei Li - Newcastle WA, US
Robert G. Blankenship - Tacoma WA, US
Robert J. Safranek - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 13/40
G06F 13/42
G06F 13/12
G06F 15/173
G06F 1/10
Abstract:
Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.

Multichip Package Link

View page
US Patent:
20180300275, Oct 18, 2018
Filed:
Nov 22, 2017
Appl. No.:
15/821492
Inventors:
- Santa Clara CA, US
Mahesh Wagh - Portland OR, US
Debendra Das Sharma - Saratoga CA, US
Gerald S. Pasdast - San Jose CA, US
Ananthan Ayyasamy - Beaverton OR, US
Xiaobei Li - Newcastle WA, US
Robert G. Blankenship - Tacoma WA, US
Robert J. Safranek - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 13/40
G06F 1/10
Abstract:
Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.

Multichip Package Link

View page
US Patent:
20170083475, Mar 23, 2017
Filed:
Dec 26, 2013
Appl. No.:
15/039452
Inventors:
- Santa Clara CA, US
Mahesh Wagh - Portland OR, US
Debendra Das Sharma - Saratoga CA, US
Gerald S. Pasdast - San Jose CA, US
Ananthan Ayyasamy - Beaverton OR, US
Xiaobei Li - Newcastle WA, US
Robert G. Blankenship - Tacoma WA, US
Robert J. Safranek - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 13/42
G06F 15/173
G06F 13/12
Abstract:
Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.
Control profile
Ananthan Ayyasamy from Portland, OR, age ~48 Get Report