Amaury A Gendron

8242566, Aug 14, 2012

Jan 19, 2010

12/689666

Rouying Zhan - Gilbert AZ, US
Amaury Gendron - Scottsdale AZ, US
Chai Ean Gill - Chandler AZ, US

Freescale Semiconductors, Inc. - Austin TX

H01L 21/8222

257355, 257106, 257E21608, 361 56

A stacked electrostatic discharge (ESD) protection clamp (-) for protecting associated devices or circuits () comprises two or more series coupled (stacked) bipolar transistors () whose individual trigger voltages Vt depend on their base-collector spacing D. A first (--) of the transistors () has a spacing Dchosen within a D range Z whose slope (ΔVt/ΔD) has a first value (ΔVt/ΔD), and a second (--) of the transistors () has a spacing value Dchosen within a D range Z or Z whose slope (ΔVt/ΔD) has a second value (ΔVt/ΔD)less than the first value (ΔVt/ΔD). The sensitivity of the ESD stack trigger voltage Vtto base-collector spacing variations ΔD during manufacture is much reduced, for example, by as much as 50% for a 2-stack and more for 3-stacks and beyond. A wide range of Vtvalues can be obtained that are less sensitive to unavoidable manufacturing spacing variations ΔD.

8390071, Mar 5, 2013

Nov 30, 2010

12/956686

Rouying Zhan - Gilbert AZ, US
Amaury Gendron - Scottsdale AZ, US
Chai Ean Gill - Chandler AZ, US

Freescale Semiconductor, Inc. - Austin TX

H01L 23/62
H01L 21/8222

257361, 438331

A stackable electrostatic discharge (ESD) protection clamp () for protecting a circuit core () comprises, a bipolar transistor () having a base region () with a base contact () therein and an emitter () spaced a lateral distance Lbe from the base contact (), and a collector () proximate the base region (). The base region () comprises a first portion () including the base contact () and emitter (), and a second portion () with a lateral boundary () separated from the collector () by a breakdown region () whose width D controls the clamp trigger voltage, the second portion () lying between the first portion () and the boundary (). The damage-onset threshold current It of the ESD clamp () is improved by increasing the parasitic resistance Rbe of the emitter-base region (), by for example, increasing Lbe or decreasing the relative doping density of the first portion () or a combination thereof.

8390092, Mar 5, 2013

Nov 12, 2010

12/944931

Amaury Gendron - Scottsdale AZ, US
Chai Ean Gill - Chandler AZ, US
Vadim A. Kushner - Tempe AZ, US
Rouying Zhan - Gilbert AZ, US

Freescale Semiconductor, Inc. - Austin TX

H01L 23/58

257487, 257111, 257577, 257E21042, 257E21051, 257E21058, 257E21126, 257E21127, 257E21135, 257E21608, 438289, 438328

An area-efficient, high voltage, single polarity ESD protection device () is provided which includes an p-type substrate (); a first p-well (-) formed in the substrate and sized to contain n+ and p+ contact regions () that are connected to a cathode terminal; a second, separate p-well (-) formed in the substrate and sized to contain only a p+ contact region () that is connected to an anode terminal; and an electrically floating n-type isolation structure (-) formed in the substrate to surround and separate the first and second semiconductor regions. When a positive voltage exceeding a triggering voltage level is applied to the cathode and anode terminals, the ESD protection device triggers an inherent thyristor into a snap-back mode to provide a low impedance path through the structure for discharging the ESD current.

8455306, Jun 4, 2013

May 25, 2012

13/480924

Amaury Gendron - Scottsdale AZ, US
Chai Ean Gill - Chandler AZ, US
Rouying Zhan - Gilbert AZ, US

Freescale Semiconductor, Inc. - Austin TX

H01L 21/332
H01L 21/00
H01L 27/02

438133, 438400, 438 10, 257587, 257592, 257173, 257355, 257577, 257546, 257357

Embodiments include methods for forming an electrostatic discharge (ESD) protection device coupled across input-output (I/O) and common terminals of a core circuit, where the ESD protection device includes first and second merged bipolar transistors. A base of the first transistor serves as collector of the second transistor and the base of the second transistor serves as collector of the first transistor, the bases having, respectively, first and second widths. A first resistance is coupled between an emitter and base of the first transistor and a second resistance is coupled between an emitter and base of the second transistor. ESD trigger voltage Vt and holding voltage Vh can be independently optimized by choosing appropriate base widths and resistances. By increasing Vh to approximately equal Vt, the ESD protection is more robust, especially for applications with narrow design windows, for example, with operating voltage close to the degradation voltage.

8647955, Feb 11, 2014

Feb 19, 2013

13/770548

Rouying Zhan - Gilbert AZ, US
Amaury Gendron - Scottsdale AZ, US
Chai Ean Gill - Chandler AZ, US

Freescale Semiconductor, Inc. - Austin TX

H01L 21/8222
H01L 23/62

438331, 257361

Methods for forming an electrostatic discharge protection (ESD) clamps are provided. In one embodiment, the method includes forming at least one transistor having a first well region of a first conductivity type extending into a substrate. At least one transistor is formed having another well region of a second opposite conductivity type, which extends into the substrate to partially form a collector. The lateral edges of the transistor well regions are separated by a distance D, which at least partially determines a threshold voltage Vt of the ESD clamp. A base contact of the first conductivity type is formed in the first well region and separated from an emitter of the second conductivity type by a lateral distance Lbe. The first doping density and the lateral distance Lbe are selected to provide a parasitic base-emitter resistance Rbe in the range of 1

8648419, Feb 11, 2014

Jan 20, 2010

12/690771

Amaury Gendron - Scottsdale AZ, US
Chai Ean Gill - Chandler AZ, US
Changsoo Hong - Phoenix AZ, US

Freescale Semiconductor, Inc. - Austin TX

H01L 21/331
H01L 23/62

257355, 257361, 257582, 257E2137, 257E29174

An electrostatic discharge (ESD) protection clamp () for protecting associated devices or circuits (), comprises a bipolar transistors () in which doping of facing base () and collector () regions is arranged so that avalanche breakdown occurs preferentially within a portion () of the base region () of the device () away from the overlying dielectric-semiconductor interface (). Maximum variations (ΔVt)of ESD triggering voltage Vt as a function of base-collector spacing dimensions D due, for example, to different azimuthal orientations of transistors () on a semiconductor die or wafer is much reduced. Triggering voltage consistency and manufacturing yield are improved.

20100301389, Dec 2, 2010

May 29, 2009

12/474443

Vadim A. Kushner - Tempe AZ, US
Amaury Gendron - Scottsdale AZ, US
Chai Ean E. Gill - Chandler AZ, US

H01L 29/73

257173, 257E29175, 361 56

An electrostatic discharge protection structure includes a first vertical bipolar junction transistor; a second vertical bipolar junction transistor, wherein the second vertical bipolar junction transistor has a common collector with the first vertical bipolar junction transistor, and the common collector has a first conductivity; a horizontal bipolar junction transistor wherein the collector of the horizontal bipolar junction transistor has a second conductivity that is a different conductivity than the first conductivity, and the base of the horizontal bipolar junction transistor is electrically coupled to the common collector of the first vertical bipolar junction transistor and the second vertical bipolar junction transistor; a first avalanche diode electrically coupled to the base and the collector of the first vertical bipolar junction transistor; and a second avalanche diode electrically coupled to the base and the collector of the second vertical bipolar junction transistor.

20100320501, Dec 23, 2010

Jun 18, 2009

12/487031

Amaury Gendron - Scottsdale AZ, US
Chai Ean Gill - Chandler AZ, US
Rouying Zhan - Gilbert AZ, US

FREESCALE SEMICONDUCTOR, INC. - Austin TX

H01L 29/73
H01L 21/33

257173, 438133, 257E29181, 257E21369

An electrostatic discharge (ESD) protection device () coupled across input-output (I/O) () and common () terminals of a core circuit (), comprises, first () and second () merged bipolar transistors (). A base () of the first () transistor serves as collector of the second transistor () and the base of the second transistor () serves as collector of the first () transistor, the bases () having, respectively, first width () and second width (). A first resistance () is coupled between an emitter () and base () of the first transistor () and a second resistance () is coupled between an emitter () and base () of the second transistor (). ESD trigger voltage Vt1 and holding voltage Vh can be independently optimized by choosing appropriate base widths () and resistances (). By increasing Vh to approximately equal Vt1, the ESD protection is more robust, especially for applications with narrow design windows, for example, with operating voltage close to the degradation voltage).