Resumes
Resumes
Allen Brailey Phones & Addresses
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6246 Valley View Rd, Tucson, AZ 85718 (520) 299-7557 (520) 577-7338
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Pima, AZ
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6246 N Valley View Rd, Tucson, AZ 85718 (520) 299-7557
Work
Position:
Food Preparation and Serving Related Occupations
Emails
Publications
Us Patents
Power Supply With Automatic Recovery System
View pageUS Patent:
56799853, Oct 21, 1997
Filed:
Jul 25, 1994
Appl. No.:
8/280404
Inventors:
Allen Charles Brailey - Tucson AZ
Kenneth Wayne Cash - Tucson AZ
Jack Harvey Derenburger - Tucson AZ
Kenneth Wayne Cash - Tucson AZ
Jack Harvey Derenburger - Tucson AZ
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H02J 900
US Classification:
307 18
Abstract:
A recovery system for a power supply. The inventive system includes a first circuit which detects a reapplication of wall power to the power supply and generates a signal in response thereto after an interruption in the output thereof. A second circuit then automatically reactivates the power supply on receipt of the signal without operator intervention. The invention is particularly well suited for systems having multiple power supplies each operating within an associated power boundary. In this case, a first power supply provides power to a first load and a second power supply provides power to a second load. A control circuit is provided in each load. The control circuit is equipped to receive the signal indicating a reapplication of power to a power supply within another power boundary and automatically reactivate the power supply.
Using Time Stamps To Correlate Data Processing Event Times In Connected Data Processing Units
View pageUS Patent:
54716314, Nov 28, 1995
Filed:
Oct 19, 1992
Appl. No.:
7/963347
Inventors:
Brent C. Beardsley - Tucson AZ
Allen C. Brailey - Tucson AZ
Peter L. H. Leung - Tucson AZ
Allen C. Brailey - Tucson AZ
Peter L. H. Leung - Tucson AZ
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1134
US Classification:
395650
Abstract:
A host processor(s) is loosely-coupled by a plurality of data channels to a peripheral subsystem(s). The host processor(s) has a time of day clock. The peripheral subsystem(s) has a cluster(s) that performs peripheral controller functions. Each cluster has first and second clocks that respectively generate a log entry (logging) reference time and a subsystem time. The first and second clock times result in subsystem time stamps in a log that are not related to the time of day clock. For time correlating the time of day clock with the first and second clocks, a host time stamp is generated from the time of day clock. The host time stamp is sent to the subsystem via one of the data channels for entry into the log with the current time stamps of the first and second clocks as a time-correlating entry. Queue delays in the host processor accessing a data channel for sending the host time stamp and in the subsystem for recording the time-correlating entry are compensated for by updating the host time stamp and by generating an entered time stamp at the time of recording the time-correlating entry. Time stamp correlating operations by a host processor enable recovery from a lost host time stamp.
Error Control In A Hierarchical System
View pageUS Patent:
43800670, Apr 12, 1983
Filed:
Apr 15, 1981
Appl. No.:
6/254356
Inventors:
Brent C. Beardsley - Tucson AZ
Allen C. Brailey - Pima AZ
Allen C. Brailey - Pima AZ
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1120
US Classification:
371 11
Abstract:
A hierarchical communication system has multipaths for different levels of the heirarchy, each set of paths is assigned a criticalness to the successful operation of the system. Error rates for all of the paths are monitored. A threshold for defining an unusable data path is based upon the criticalness of the path to successful operation. That is, the more critical the path, the higher the error rate that will be sustained. A specific embodiment employs shift registers for indicating the error rate of the last predetermined number of usages of the given paths. A mass storage system employing the error-rate system is described.