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Ali Sazegari Phones & Addresses

  • 447 Lerida Ave, Los Altos, CA 94024
  • Cupertino, CA
  • 835 Sheila Ct, Mountain View, CA 94043 (415) 988-1655
  • 2249 Wyandotte St, Mountain View, CA 94043 (650) 988-1547 (650) 988-1655
  • 501 Beale St #21D, San Francisco, CA 94105 (415) 978-0000
  • San Jose, CA
  • Boulder, CO
  • Santa Clara, CA

Publications

Us Patents

Handler For Floating-Point Denormalized Numbers

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US Patent:
6732134, May 4, 2004
Filed:
Sep 11, 2000
Appl. No.:
09/659747
Inventors:
Alexander Rosenberg - Saratoga CA
Ali Sazegari - Cupertino CA
Assignee:
Apple Computer, Inc. - Cupertino CA
International Classification:
G06F 738
US Classification:
708495, 708502
Abstract:
Operations that involve denormalized numbers are handled by restructuring the input values for an operation as normalized numbers, and performing calculations on the normalized numbers. As a first step in the process of performing an operation, a determination is made whether input values for the operation contain one or more denormalized numbers. For certain types of operations, a determination is made whether the input values are such that the output value from the operation will be a denormalized number. For each operation in which either the input values or output values comprise a denormalized number, the input values are scaled to produce values that are not denormalized. Once the appropriate factoring has been carried out, the requested operation is performed, using normalized numbers, to produce an intermediate result which is then adjusted to account for the initial scaling.

Matrix Multiplication In A Vector Processing System

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US Patent:
6901422, May 31, 2005
Filed:
Mar 21, 2001
Appl. No.:
09/812578
Inventors:
Ali Sazegari - Cupertino CA, US
Assignee:
Apple Computer, Inc. - Cupertino CA
International Classification:
G06F017/16
US Classification:
708607
Abstract:
The present invention is directed to a system and method for multiplication of matrices in a vector processing system. Partial products are obtained by dot multiplication of vector registers containing multiple copies of elements of a first matrix and vector registers containing values from rows of a second matrix. The dot products obtained from this dot multiplication are subsequently added to vector registers which make up a product matrix. In an embodiment of the present invention, each matrix may be divided into submatrices to facilitate the rapid and efficient multiplication of large matrices, which is done in parts by computing partial products of each submatrix. The matrix multiplication performed by the present invention avoids rounding errors as it is bit-by-bit compatible with conventional matrix multiplication methods.

Large Table Vectorized Lookup By Selecting Entries Of Vectors Resulting From Permute Operations On Sub-Tables

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US Patent:
7000099, Feb 14, 2006
Filed:
Jul 9, 2002
Appl. No.:
10/190546
Inventors:
Ali Sazegari - Cupertino CA, US
Assignee:
Apple Computer Inc. - Cupertino CA
International Classification:
G06F 9/315
US Classification:
712300, 712 4, 712 5, 712 7
Abstract:
A lookup operation is carried out on a data table by logically dividing the data table into a number of smaller sets of data that can be indexed with a single byte of data. Each set of data consists of two vectors, which constitute the operands for a permute instruction. Only a limited number of bits are required to index into the table during the execution of this instruction. The remaining bits of each index are used as masks into a series of select instructions. The select instruction chooses between two vector components, based on the mask, and places the selected components into a new vector. The mask is generated by shifting one of the higher order bits of the index to the most significant position, and then propagating that bit throughout a byte, for example by means of an arithmetic shift. This procedure is carried out for all of the index bytes in the vector, to generate a select mask. The select mask is then used during a select operation, to choose between the results of permute instructions on different ones of the logically divided sets of data.

Single-Channel Convolution In A Vector Processing Computer System

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US Patent:
7107304, Sep 12, 2006
Filed:
Nov 30, 2001
Appl. No.:
09/996877
Inventors:
Ali Sazegari - Cupertino CA, US
Doug Clarke - San Diego CA, US
Assignee:
Apple Computer, Inc. - Cupertino CA
International Classification:
G06F 7/15
US Classification:
708420
Abstract:
A system and method for performing convolution in a single channel of a vector processing computer system takes advantage of the parallel computing capability of the vector processing system and the distributed properties of the discrete-time convolution sum by performing convolution on portions of an overall data stream, or data chunks, simultaneously. Partial solution are thereby obtained and superimposed to achieve an overall solution data stream. To simplify the convolution sum and eliminate the need for calculating products, a specialized data signal or vector containing a series of ones may be used in the convolution operation.

Matrix Multiplication In A Vector Processing System

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US Patent:
7337205, Feb 26, 2008
Filed:
Apr 25, 2005
Appl. No.:
11/113035
Inventors:
Ali Sazegari - Cupertino CA, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
G06F 17/16
US Classification:
708607
Abstract:
To perform multiplication of matrices in a vector processing system, partial products are obtained by dot multiplication of vector registers containing multiple copies of elements of a first matrix and vector registers containing values from rows of a second matrix. The dot products obtained from this dot multiplication are subsequently added to vector registers which form a product matrix. Each matrix can be divided into submatrices to facilitate the rapid and efficient multiplication of large matrices, which is done in parts by computing partial products of each submatrix. The matrix multiplication avoids rounding errors as it is bit-by-bit compatible with conventional matrix multiplication methods.

Computation Of Power Functions Using Polynomial Approximations

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US Patent:
7668894, Feb 23, 2010
Filed:
Aug 22, 2003
Appl. No.:
10/645555
Inventors:
Ali Sazegari - Cupertino CA, US
Ian Ollmann - Mountain View CA, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
G06F 1/02
US Classification:
708270, 708272
Abstract:
A power function is approximated over an applicable data interval with polynomials determined by means of a Chebyshev minimax approximation technique. In some cases, multiple polynomials may be used to approximate the function over respective ranges of the desirable interval, in a piecewise manner. The appropriate polynomial that approximates the power function over the range of interest is derived and stored. When the power function is to be applied to a particular data value, the data value is first evaluated to determine where it lies within the applicable interval. The constants for the polynomial associated with that range of the interval are then retrieved and used to calculate the power of that data value.

Single-Channel Convolution In A Vector Processing Computer System

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US Patent:
7895252, Feb 22, 2011
Filed:
Sep 12, 2006
Appl. No.:
11/518916
Inventors:
Ali Sazegari - Cupertino CA, US
Doug Clarke - San Diego CA, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
G06F 7/15
US Classification:
708420
Abstract:
A system and method for performing convolution in a single channel of a vector processing computer system takes advantage of the parallel computing capability of the vector processing system and the distributed properties of the discrete-time convolution sum by performing convolution on portions of an overall data stream, or data chunks, simultaneously. Partial solution are thereby obtained and superimposed to achieve an overall solution data stream. To simplify the convolution sum and eliminate the need for calculating products, a specialized data signal or vector containing a series of ones may be used in the convolution operation.

Compiling Techniques For Providing Limited Accuracy And Enhanced Performance Granularity

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US Patent:
8370822, Feb 5, 2013
Filed:
Nov 20, 2008
Appl. No.:
12/275178
Inventors:
Ali Sazegari - Cupertino CA, US
Stephen Tyrone Canon - Palo Alto CA, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
G06F 9/45
US Classification:
717152, 717151, 717154
Abstract:
A programmable compiler detects from source code invocations of math functions that require reduced levels of accuracy, limited variable domains, or enhanced performance. The programmable compiler replaces such invocations with intrinsics from the compiler's own intrinsic library. The math function invocations are compiled into inline object code. The inline object can be subsequently optimized along with other object code through normal compiler optimization. If an accuracy requirement is beyond what any compiler intrinsic can provide, the programmable compiler preserves the invocation of the math function defined in a default library.
Ali Sazegari from Los Altos, CA, age ~67 Get Report