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Alexander K Spencer

from Austin, TX
Age ~65
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Also known as:
Alexander Koos Spencer, Alexander Te Spencer, Alexander E Spencer, Alex K Spencer, Alex E Spencer, Alexander K Diane, Alen Spencer, Alex Alex, Klaus Spencer Alexander, Spencer Alexander
Phone and address:
11412 Rustic Rock Dr, Austin, TX 78750
(512) 331-0994
Related to:
Craig E Spencer, 65Leo WingateThomas A SpencerDiane WingateF L Wingate, 66Shirley L WingateWoody SpencerGertrude K Spencer, 96L Wingate, 71Diane E Spencer, 66Martha E Wingate, 71Shirley WingateLeo K Wingate, 72Francis L Wingate, 71
Connected to:
Addison H Spencer, 41Admensa J Spencer, 78Ahmal Spencer, 48Alannah M Spencer, 31Alden A Spencer, 52Alex Spencer, 45Alison D Spencer, 45Allan Spencer, 31Allie Spencer, 40Alonda J Spencer, 59

Alexander Spencer Phones & Addresses

  • 11412 Rustic Rock Dr, Austin, TX 78750 (512) 331-0994
  • Burnet, TX
  • Flint, TX
  • Fort Davis, TX
  • Tow, TX
  • Travis, TX
  • Llano, TX
  • 11412 Rustic Rock Dr, Austin, TX 78750 (512) 762-3896

Work

Position: Executive, Administrative, and Managerial Occupations

Education

Degree: Graduate or professional degree

Resumes

Resumes

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Alexander Spencer

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Location:
Austin, Texas Area
Industry:
Computer Hardware
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Seminole High School

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Work:

Seminole High School
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Alexander Spencer

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Alexander Spencer

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Mechanical Or Industrial Engineering Professional

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Location:
Austin, Texas Area
Industry:
Mechanical or Industrial Engineering
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Alexander Spencer

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Alexander Spencer

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Alexander Spencer

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Publications

Us Patents

Method And System For Analyzing Wire-Only Changes To A Microprocessor Design Using Delta Model

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US Patent:
6405352, Jun 11, 2002
Filed:
Jun 30, 1999
Appl. No.:
09/343448
Inventors:
Alexander Koos Spencer - Austin TX
Barry Duane Williamson - Round Rock TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1750
US Classification:
716 6
Abstract:
A method for analyzing a design or a model of a microprocessor chip model is provided. A base chip model is generated, and it is modified with wire-only changes to produce a modified chip model. The modified chip model is compared to the base chip model to discern the wire-only changes to form a delta chip model. A set of values for RC delays and net capacitance based on the delta chip model is produced, and the modified chip model is timed using the set of values for RC delays and net capacitance on the delta chip model and RC delays and net capacitance on the base chip model.

Post-Manufacture Signal Delay Adjustment To Solve Noise-Induced Delay Variations

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US Patent:
6532574, Mar 11, 2003
Filed:
Aug 17, 2000
Appl. No.:
09/640537
Inventors:
Christopher McCall Durham - Round Rock TX
Sharad Mehrotra - Austin TX
Alexander Koos Spencer - Austin TX
Barry Duane Williamson - Cedar Park TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1750
US Classification:
716 6, 716 5
Abstract:
Adjacent signal lines within the critical path of logic within an integrated circuit are checked for capacitive coupling induced signal delay variations resulting from concurrent signal transitions. When found, signal transition overlap is eliminated by delaying the clock edge (rising or falling) triggering the signal driving logic, without necessarily delaying the other clock edge. A delay circuit is incorporated into clock stages for the signal driving logic, and may be selectively actuated to delay the clock edge to particular signal driving logic circuits. Selection of signal lines in which signal transitions are to be delayed may be performed after manufacture of the integrated circuit, and iterative determinations may be required since signal adjustment may create new critical paths within the integrated circuit logic. Once the final signal adjustment configuration is determined, that configuration may be stored as a vector within a memory in the integrated circuit and read during power-up into a scan chain controlling the individual delay circuits.

Graphics Display System Function Circuit

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US Patent:
48375632, Jun 6, 1989
Filed:
Feb 12, 1987
Appl. No.:
7/013841
Inventors:
Robert L. Mansfield - Austin TX
Alexander K. Spencer - Austin TX
Joe C. St. Clair - Round Rock TX
Assignee:
International Business Machine Corporation - Armonk NY
International Classification:
G09G 100
US Classification:
340732
Abstract:
In a graphics display system a counter for performing either a line drawing algorithm or a bit block transfer algorithm where the counter is performing the bit block transfer algorithm includes a first counter circuit counting from a first initial state to a first predetermined value and a second counter circuit counting from a second initial state to a second predetermined value. The second counter counts in response to the first counter reacing to its predetermined value. In support of a line drawing algorithm, the counter circuit reconfigures itself to provide a first counter to count from its first initial state to the first predetermined value and a second counter to compute a parameter value and to conditionally count from a second initial value to a second predetermined value in response to the value of this parameter. These counters are connected to an addressing circuit to increment the addresses in performance of the algorithms. This counter circuit capability increases the speed at which line draw functions and bit block transfer functions can be accomplished in a graphics display system processor.

Look Ahead Bus Transfer Request

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US Patent:
51797097, Jan 12, 1993
Filed:
Nov 14, 1990
Appl. No.:
7/611380
Inventors:
Roger N. Bailey - Austin TX
Robert L. Mansfield - Austin TX
Alexander K. Spencer - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1300
US Classification:
395725
Abstract:
A technique for use in an I/O channel to increase bus bandwidth during DMA data transfers between main system memory and a communication link is disclosed, including a pair of buffers, a plurality of counters adapted to selectively contain a count of data increments therein, and enhanced DMA control logic for monitoring buffer data content amount, and at a predetermined time during a given transfer initiating a bus arbitration so that it is completed simultaneously with the given transfer, thereby enabling the next data transfer from the buffer in use to immediately commence.

System And Method For Saving State Information In A Multi-Execution Unit Processor When Interruptable Instructions Are Identified

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US Patent:
54407036, Aug 8, 1995
Filed:
Sep 20, 1993
Appl. No.:
8/123816
Inventors:
David S. Ray - Georgetown TX
Alexander K. Spencer - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 930
G06F 938
US Classification:
395375
Abstract:
An apparatus and method provides additional logic in both execution units of a dual execution unit processing in order to determine if the instruction is interruptable. Additionally, backout logic is provided for saving the contents of unique registers. The backout logic uses two decodes to determine if the instruction currently executing modifies the unique registers. It is possible for a single instruction to modify more than one unique register. The backout logic of the present invention resides in both of the execution units and particularly in the unit which contains the unique register being modified by the executing instruction. If an instruction is being executed which modifies one of the unique registers, then the contents of that register are saved in a backout latch. A cancel signal is then provided if the interruptable instruction executes without causing an interrupt. However, if the interruptable instruction does cause an interrupt, then the contents of the backout latch are reloaded into the execution units.

Pixel Data Path For High Performance Raster Displays With All-Point-Addressable Frame Buffers

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US Patent:
48232866, Apr 18, 1989
Filed:
Feb 12, 1987
Appl. No.:
7/013847
Inventors:
Leon Lumelsky - Stamford CT
Joe C. St. Clair - Round Rock TX
Robert L. Mansfield - Austin TX
Marc Segre - Rhinebeck NY
Alexander K. Spencer - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1206
US Classification:
364521
Abstract:
A multichannel data path architecture which assists a host processor in communication with the frame buffer in order to increase the overall system performance. The architecture provides automatic frame buffer data path rearrangement depending on the pixel address and the host data interpretation. It utilizes a minimum of shift registers, accumulators and control circuitry to provide the requisite storage, reconfiguration and frame buffer access functions. The architecture extends bit-blt (bit block transfer) conventional operations in order to provide high quality "antialiased" text and graphics directly in the architecture without requiring the calculation of colors by the host processor. Finally, it assists the "burst" mode update of an arbitrary single plane of a frame buffer, which is especially important when high denisty chips are used for the frame buffer implemenation.

Multiple Event Timer Circuit

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US Patent:
50124358, Apr 30, 1991
Filed:
Nov 17, 1988
Appl. No.:
7/273295
Inventors:
Roger N. Bailey - Austin TX
Robert L. Mansfield - Austin TX
Alexander K. Spencer - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 918
G04B 2312
US Classification:
364569
Abstract:
A timer including a counter circuit that continuously provides an output of an iteratively increasing sequence of bits. The timer includes a timeout data circuit that forms a timeout data word from a specified time period and a first counter circuit output. A register is provided that stores the timeout data word at an address formed from a second counter circuit output. A comparison circuit is provided that compares each counter output with a timeout data word at the address formed from that counter output and provides a timeout signal when they are equal. This timer includes a constantly incrementing counter to address a register that includes a multiple of timeout condition specifications, and as a determination of when the timeout conditions stored in the register occur.

High Resolution Graphics Display Adapter

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US Patent:
48704067, Sep 26, 1989
Filed:
Feb 12, 1987
Appl. No.:
7/013842
Inventors:
Satish Gupta - Peekskill NY
Leon Lumelsky - Stamford CT
Robert L. Mansfield - Austin TX
Hector G. Romero - Austin TX
Marc Segre - Rhinebeck NY
Alexander K. Spencer - Austin TX
Joe C. St. Clair - Round Rock TX
James D. Wagoner - Georgetown TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G09G 128
US Classification:
340 70
Abstract:
A display adapter for displaying graphics data in pixel form on a high resolution display monitor includes a digital signal processor for managing adapter resources and controlling coordinate transformations, a system storage which is divided into a first portion for storing instructions for the digital signal processor and the second portion for storing data representing information to be displayed, an input buffer for permitting asynchronous and overlapped communication between the graphics display adapter and a host computer to speed operation of the system, a pixel processor for drawing vectors and manipulating areas to be displayed on the monitor, a bit mapped frame buffer, a color palette connected to outputs of the frame buffer for providing appropriate color signals to the high resolution monitor and a cursor circuit for controlling display of a cursor on the screen on the monitor.
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Alexander K Spencer from Austin, TX, age ~65 Get Report