Alexander G Frey

43995071, Aug 16, 1983

Jun 30, 1981

6/280417

Michael R. Cosgrove - late of Haymarket VA
Alexander H. Frey - Cabin John MD
Kenneth A. Moore - Manassas VA
Abraham Peled - San Jose CA
Frederic N. Ris - Mohegan Lake NY
William W. Sproul - Reston VA

IBM Corporation - Armonk NY

G06F 928

364200

An instruction pipeline for a data processor is disclosed, in which instruction execution is carried out in a sequence of phases which include fetching the instruction from an instruction storage, computing a data storage address from the fetched instruction, accessing the data storage at the computed address to obtain a datum operand, and then carrying out the logical or arithmetic operation on the accessed datum in accordance with the fetched instruction. Branch and stack instructions and return instructions are accommodated by providing a return address stack in the data storage, which stores the next instruction store address to be returned to after a return operation has been completed. Since the instruction address stack in the data storage cannot be directly accessed by the instruction fetching stage of the pipeline until several instruction execution phases have transpired, without degrading the performance of the pipeline, a stack register is provided in the instruction fetch stage of the pipeline which contains a duplicate of the instruction store address presently residing at the top of the instruction address stack. Then when a return instruction is encountered in the instruction fetch stage, the address of the next instruction to be returned to in the instruction storage is immediately available without interrupting the flow in the pipeline.

46384499, Jan 20, 1987

Aug 14, 1985

6/765567

Alexander H. Frey - Cabin John MD

International Business Machines Corporation - Armonk NY

G06F 752

364760

An improved multiplier is disclosed for multiplying a first operand times a second operand, which includes a Booth-type translator having an input connected to receive the first operand, for translating the binary expression of the first operand into a sequence of signed digits. The multiplier further includes a partial product generator having a first input connected to the output of the translator and a second input connected to receive the second operand, for multiplying the translated first operand times the second operand and outputting partial products consisting of signed digits. The multiplier further includes an array of adders, each adder having an input connected to two of the signed digits output from the partial product generator, for providing a sum consisting of a sequence of signed digits. The multiplier further includes an inverse translator having an input connected to the output of the adders, for operating on the sequence of signed digits output from the adders, for providing a conventional binary expression for the product of the first and the second operands. The improved multiplier is capable of faster operation than has been available in the prior art.