Resumes
Resumes
Principal Engineer , Asic Design
View pageLocation:
92 Dearwell Way, San Jose, CA 95138
Industry:
Computer Hardware
Work:
Western Digital
Principal Engineer , Asic Design
Synopys Feb 2014 - Aug 2018
Senior Cae
Lsi Corporation Oct 2010 - Jan 2014
Staff Design Engineer
Gda Technologies Aug 2000 - Sep 2010
Member Technician Staff
Principal Engineer , Asic Design
Synopys Feb 2014 - Aug 2018
Senior Cae
Lsi Corporation Oct 2010 - Jan 2014
Staff Design Engineer
Gda Technologies Aug 2000 - Sep 2010
Member Technician Staff
Education:
San Jose State University 2004 - 2006
Master of Science, Masters
Master of Science, Masters
Skills:
Rtl Design
Soc
Asic
Debugging
Embedded Systems
Verilog
Systemverilog
Fpga
Ic
Hardware Architecture
Integrated Circuit Design
Vlsi
Static Timing Analysis
Pcie
Functional Verification
Serdes
Rtl Coding
Eda
Signal Integrity
Device Drivers
Modelsim
Arm
Usb
Soc
Asic
Debugging
Embedded Systems
Verilog
Systemverilog
Fpga
Ic
Hardware Architecture
Integrated Circuit Design
Vlsi
Static Timing Analysis
Pcie
Functional Verification
Serdes
Rtl Coding
Eda
Signal Integrity
Device Drivers
Modelsim
Arm
Usb
Languages:
English
Alex Jose
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Alex Jose
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Alex Jose
View pageLocation:
United States