Inventors:
Daniel C. Espinosa - North Bethesda MD, US
Alessandro Geist - Bethesda MD, US
Daivd J. Petrick - Severna Park MD, US
Thomas P. Flatley - Huntington MD, US
Jeffrey C. Hosler - Annapolis MD, US
Gary A. Crum - Silver Spring MD, US
Manuel Buenfil - Olney MD, US
International Classification:
G06F 11/16
G06F 12/00
US Classification:
714 54, 711103, 714E11056
Abstract:
A processing system including an FPGA having a dual port RAM and for use in hostile environments. The FPGA includes three portions: a C&DH portion; a first scratch pad portion receiving a first set of data, processing the first set of data, and outputting a first set of processed data to a first location of the RAM; and a second scratch pad portion receiving a second set of data identical to the first set of data, processing the second set of data in the same way that the first set of data is processed, and outputting a second set of processed data to a second location of the RAM. The C&DH portion compares the first set of processed data to the second set of processed data and, if the first set of processed data is the same as the second set of processed data, outputs one set of processed data.