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Albert M Scalise

from San Jose, CA
Age ~65
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Also known as:
Albert Michael Scalise, Ambert M Scalise, Al Scalise
Phone and address:
3107 Elaine Dr, San Jose, CA 95124
(408) 504-6161
Related to:
Bridget Patrick O'Sullivan, 79Deborah L Kirk, 61Christopher Scalise, 67Janice Boyd, 68Mary Scalise, 70Glenn M Scalise, 63
Connected to:
Amanda Scalise, 38Bryan J Scalise, 42Damien Y Scalise, 33Danielle M Scalise, 35Dominic W Scalise, 60Janet H Scalise, 55Judie A Scalise, 73Marcella L Scalise, 32Martin G Scalise, 52Michael Scalise, 72

Albert Scalise Phones & Addresses

  • 3107 Elaine Dr, San Jose, CA 95124 (408) 504-6161
  • Campbell, CA
  • Sunnyvale, CA
  • Fontana, CA
  • 3107 Elaine Dr, San Jose, CA 95124

Work

Position: Service Occupations

Emails

s***[email protected]

Publications

Us Patents

Methods And Apparatus For Variable Length Sdram Transfers

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US Patent:
6385692, May 7, 2002
Filed:
Mar 12, 2001
Appl. No.:
09/805588
Inventors:
Jano D. Banks - Cupertino CA
Dale R. Adams - San Jose CA
Albert M. Scalise - San Jose CA
Assignee:
Silicon Image, Inc. - Sunnyvale CA
International Classification:
G06F 1200
US Classification:
711105, 711 5, 711158
Abstract:
Disclosed is a SDRAM system including a SDRAM having multiple banks of memory, a plurality of bank state machines associated the multiple banks of memory of the SDRAM, and a data control state machine. The data state machine is responsive to a memory request for a variable length data transfer with the SDRAM and as well as the bank state machines. The data control state machine determines the current state of a first bank of memory of the SDRAM. The current state may be either a read in progress, a write in progress, or idle. The data control state machine then handles the memory request with a different bank of memory RAM depending upon the current state of the first bank of memory.

Methods And Apparatus For Data Bus Arbitration

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US Patent:
6393505, May 21, 2002
Filed:
Jan 6, 1999
Appl. No.:
09/227502
Inventors:
Albert M. Scalise - San Jose CA
Jano D. Banks - Cupertino CA
Assignee:
DVDO, Inc. - Sunnyvale CA
International Classification:
G06F 1300
US Classification:
710107, 710 40, 710113, 710240, 710241, 710244
Abstract:
A data bus arbitration system is disclosed including a bus status monitor which is coupled to a data bus and generates a bus status signal for use by an arbiter. The arbiter is coupled to a number of requesters, each of which belongs to a distinct class of requesters. The arbiter arbitrates between multiple requests using heuristics dependent upon the classes of the requesters. The nature of one class of requestors is that the requestors have real time requirements which must be met in order to maintain data integrity within the system. The nature of a second class of requestors is such that the requestors have semi-real time requirements which must be met in order to maintain data integrity within the system. The nature of the system is such that the available bandwidth must be utilized very efficiently in order to maintain data integrity within the system. The arbiter system disclosed grants access to the requesters using the heuristics disclosed while maintaining an efficiency of at least 80% of the total bandwidth for all requestors.

Method And System For Video And Auxiliary Data Transmission Over A Serial Link

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US Patent:
6914637, Jul 5, 2005
Filed:
Jul 10, 2002
Appl. No.:
10/192296
Inventors:
Paul Daniel Wolf - San Carlos CA, US
John D. Banks - Cupertino CA, US
Stephen J. Keating - Sunnyvale CA, US
Duane Siemens - Mountain View CA, US
Eric Lee - San Jose CA, US
Albert M. Scalise - San Jose CA, US
Gijung Ahn - San Jose CA, US
Seung Ho Hwang - Palo Alto CA, US
Keewook Jung - Santa Clara CA, US
James D. Lyle - Santa Clara CA, US
Michael Anthony Schumacher - San Jose CA, US
Vladimir Grekhov - Los Altos CA, US
Assignee:
Silicon Image, Inc. - Sunnyvale CA
International Classification:
H04N007/52
US Classification:
348473, 348476
Abstract:
A communication system including a transmitter, a receiver, and a serial link, in which encoded data (e. g. , video, audio, and optionally also other auxiliary data) are transmitted from the transmitter to the receiver. The serial link can but need not be a TMDS or TMDS-like link. In typical embodiments, packets of encoded audio data are transmitted over each of one or more channels of the link during data islands between bursts of encoded video data. Other aspects of the invention are transmitters for use in encoding data for transmission over a serial link, receivers for receiving such data, and methods for sending encoded data over a serial link.

Method And Apparatus For Regenerating A Clock For Auxiliary Data Transmitted Over A Serial Link With Video Data

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US Patent:
7088398, Aug 8, 2006
Filed:
Jun 14, 2002
Appl. No.:
10/171860
Inventors:
Paul Daniel Wolf - San Carlos CA, US
Adrian Sfarti - Cupertino CA, US
John D. Banks - Cupertino CA, US
Stephen J. Keating - Sunnyvale CA, US
Duane Siemens - Mountain View CA, US
Eric Lee - San Jose CA, US
Albert M. Scalise - San Jose CA, US
Gijung Ahn - Sunnyvale CA, US
Seung Ho Hwang - Palo Alto CA, US
Keewook Jung - Santa Clara CA, US
Assignee:
Silicon Image, Inc. - Sunnyvale CA
International Classification:
H04N 7/08
H04N 7/12
H04N 7/52
US Classification:
3484231, 348473, 348478, 348465, 348515, 3484254, 37524028
Abstract:
A communication system including a transmitter, a receiver, and a serial link, in which encoded data (e. g. , video, audio, and optionally also other auxiliary data) are transmitted from the transmitter to the receiver. The serial link can but need not be a TMDS or TMDS-like link. In typical embodiments, packets of encoded audio data are transmitted over each of one or more channels of the link during data islands between bursts of encoded video data, a pixel clock is transmitted over the link, and the receiver regenerates a clock for the audio data using time code data in the packets and the pixel clock. Other aspects of the invention are transmitters for transmitting encoded data and a pixel clock over a serial link, receivers for receiving such data and pixel clock and performing audio clock regeneration, and methods for transmitting encoded data and a pixel clock over a serial link and performing clock regeneration using the transmitted data and pixel clock.

Method And System For Reducing Inter-Symbol Interference Effects In Transmission Over A Serial Link With Mapping Of Each Word In A Cluster Of Received Words To A Single Transmitted Word

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US Patent:
7257163, Aug 14, 2007
Filed:
Mar 12, 2002
Appl. No.:
10/095422
Inventors:
Seung Ho Hwang - Palo Alto CA, US
Jano Banks - Cupertino CA, US
Paul Daniel Wolf - San Carlos CA, US
Eric Lee - San Jose CA, US
William Sheet - Fremont CA, US
Albert M. Scalise - San Jose CA, US
Assignee:
Silicon Image, Inc. - Sunnyvale CA
International Classification:
H04B 14/04
US Classification:
375242, 375346, 348473, 348476
Abstract:
A system in which encoded data (e. g. , encoded video and auxiliary data) are transmitted over a serial link. Other aspects of the invention are transmitters for use in encoding data for transmission over a serial link, receivers for receiving such data, and methods for sending encoded data over a serial link. Source data to be transmitted are encoded using a subset of a full set of code words. The subset consists of preferred code words. Disjoint clusters of code words in the full set are predetermined. Each cluster includes one or more of the preferred words, and optionally also at least one additional code word that is similar to a preferred word of the cluster in the sense that it is likely to be generated as a result of probable bit errors in transmission, or transmission and decoding, of such preferred word. Each preferred word of a cluster is indicative of a single source data value. Each received code word in a cluster is mapped to the source data value determined by each preferred word of the cluster.

Encoding Method And System For Reducing Inter-Symbol Interference Effects In Transmission Over A Serial Link

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US Patent:
7359437, Apr 15, 2008
Filed:
Dec 24, 2001
Appl. No.:
10/036234
Inventors:
Seung Ho Hwang - Palo Alto CA, US
Jano Banks - Cupertino CA, US
Paul Daniel Wolf - San Carlos CA, US
Eric Lee - San Jose CA, US
Baegin Sung - Sunnyvale CA, US
Albert M. Scalise - San Jose CA, US
Assignee:
Silicon Image, Inc. - Sunnyvale CA
International Classification:
H04B 1/66
US Classification:
375240, 37524001, 37524023, 375246, 375254, 375296, 3484231, 348470
Abstract:
A communication system including a transmitter, a receiver, and a serial link, in which encoded data (e. g. , encoded video data and encoded auxiliary data) are transmitted from the transmitter to the receiver. The serial link can but need not be a TMDS or TMDS-like link. In typical embodiments, alternating bursts of encoded video data and encoded auxiliary data are transmitted over each of one or more channels of the link. Other aspects of the invention are transmitters for use in encoding data for transmission over a serial link, and methods for sending encoded data over a serial link. In accordance with the invention, the data to be transmitted are encoded using a subset (sometimes referred to as a selected set of code words) of a full set of code words. The selected set of code words is selected such that each stream of encoded data (comprising only such code words) transmitted over a serial link has a bit pattern that is less susceptible to inter-symbol interference (“ISI”) during transmission than is the bit pattern determined by a conventionally encoded version of the same data (comprising not only the selected set of code words but also other members of the full set). In general, the best choice for the selected set of code words selected from a full set of binary code words depends on the particular coding implemented by the full set.

Asic Cell Implementation Of A Bus Controller With Programmable Timing Value Registers For The Apple Desktop Bus

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US Patent:
58288570, Oct 27, 1998
Filed:
Jan 5, 1996
Appl. No.:
8/583375
Inventors:
Albert M. Scalise - San Jose CA
Assignee:
Apple Computer, Inc. - Cupertino CA
International Classification:
G06F 1300
US Classification:
395309
Abstract:
An ASIC (Application Specific Integrated Circuit) cell implementation of an ADB (Apple Desktop Bus) bus controller with programmable timing value registers for the Apple Desktop Bus (ADB) has a system interface for connecting to a computer system including an address bus interface, a data bus interface, and a control bus interface, and has an ADB interface for connecting to an ADB peripheral bus. A control state machine within the ADB bus controller uses timing data from the programmable timing value registers to implement the Apple Desktop Bus data signaling and communications protocol on the ADB interface.

Clock And Counter For Bit Cell Determination And Timeout Timing For Serial Data Signaling On An Apple Desktop Bus

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US Patent:
57782016, Jul 7, 1998
Filed:
Jan 26, 1996
Appl. No.:
8/591855
Inventors:
Albert M. Scalise - San Jose CA
International Classification:
G06F 1300
US Classification:
395306
Abstract:
A method for bit cell determination and timeout detection for an Apple Desktop Bus, using a counter clocked by a clock generator, according to the steps of: At the start of a bit cell, loading an initial value into the counter and enabling the counter to count down as clocked by the clock generator. Counting down until a low to high transition in the input ADB signal is detected or a terminal count is reached, such that if the low to high transition transition is detected, then enabling the counter to count up, else if the terminal count is reached, then indicating a timeout condition. If the counter is enabled to count up, then counting up until a high to low transition in the input ADB signal is detected or the terminal count is reached, such that if the high to low transition is detected, then stopping the counter and reading a final value to determine the bit cell value, else if the terminal count is reached, then indicating a timeout condition.
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Albert M Scalise from San Jose, CA, age ~65 Get Report