Search

Alan L Kordick

from Allen, TX
Age ~58
Get Report
Also known as:
Alan Lee Kordick, Alan K
Phone and address:
1019 Monroe St, Allen, TX 75002
(972) 396-9113
Related to:
Marvin M Sladek, 87Marcella L SladekRobyn L Kordick, 56
Connected to:
John M Kordich, 39Ann K Kording, 35Robert L Kording, 75Christopher J Kordish, 59Kassandra M Kordish, 33Rebecca D Kordish, 42Robin L Kordish, 39William A Kordish, 78Erin M Kordon, 39Laura C Kordon, 56

Alan Kordick Phones & Addresses

  • 1019 Monroe St, Allen, TX 75002 (972) 396-9113 (972) 396-9116
  • Ames, IA
  • Richardson, TX
  • Gilbert, IA

Publications

Us Patents

Method For Fabricating A P-Type Shallow Junction Using Diatomic Arsenic

View page
US Patent:
20040224470, Nov 11, 2004
Filed:
May 5, 2003
Appl. No.:
10/429796
Inventors:
Tim Makovicka - McKinney TX, US
Alan Kordick - Allen TX, US
Assignee:
Texas Instruments, Incorporated - Dallas TX
International Classification:
H01L021/336
H01L021/425
US Classification:
438/299000, 438/306000, 438/528000, 438/530000
Abstract:
The present invention provides, in one embodiment, a method of fabricating a semiconductor device (). The method comprises exposing a portion () of an n-type substrate () to an arsenic dimer (). The method also includes forming a p-type lightly doped drain (LDD) region () within the portion of the n-type substrate (). Other embodiments advantageously incorporate the method into methods for making PMOS devices.

Method For Fabricating A P-Type Shallow Junction Using Diatomic Arsenic

View page
US Patent:
20060011987, Jan 19, 2006
Filed:
Sep 20, 2005
Appl. No.:
11/230608
Inventors:
Tim Makovicka - McKinney TX, US
Alan Kordick - Allen TX, US
International Classification:
H01L 29/94
H01L 21/8238
US Classification:
257369000, 438199000
Abstract:
The present invention provides, in one embodiment, a method of fabricating a semiconductor device (). The method comprises exposing a portion () of an n-type substrate () to an arsenic dimer (). The method also includes forming a p-type lightly doped drain (LDD) region () within the portion of the n-type substrate (). Other embodiments advantageously incorporate the method into methods for making PMOS devices.

Methods For Monitoring Implanter Performance

View page
US Patent:
20090166564, Jul 2, 2009
Filed:
Dec 31, 2007
Appl. No.:
11/968089
Inventors:
BENJAMIN G. MOSER - Chandler AZ, US
John E. Wiggins - Royce City TX, US
Jeffrey G. Loewecke - Wylle TX, US
Alan L. Kordick - Allen TX, US
Richard L. Guldi - Dallas TX, US
International Classification:
G21K 5/10
US Classification:
25049221
Abstract:
Methods are presented to monitor the performance of an ion implanter such as the E500. Ion implantation typically involves physical processes performed on a wafer such as rotation, tilt, and twist. These methods generate particulate contaminants (PCs) that affect the kill rate of the semiconductor devices on the wafer. Variations in tilt angle also compromise dose accuracy. Presently, methods for testing for PCs and implant dose accuracy do not simulate actual manufacturing conditions. This invention discloses methods to test PC buildup using multiple wafers that are subjected to rotation, twist, tilt, and combinations thereof. Additionally, methods to test dose accuracy are presented, involving implanting a monitor wafer at an angle where the crystalline channel is aligned with the ion beam. Measuring sheet resistance as a function of tilt angle at this point ensures accurate tilt-angle calibration of the ion implanter.
Control profile
Alan L Kordick from Allen, TX, age ~58 Get Report