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Chit A Mak

from San Jose, CA
Age ~73
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Also known as:
Chit Ah Mak, Chit Sylvia Mak, Ah Mak Chit, Chit Ah Te Mak, Mak Chit, Chit Ah T, Chitah Mak, H Mak, Mah Chit
Phone and address:
577 Rough And Ready Rd, San Jose, CA 95133
(510) 623-7342
Related to:
Qiao X Mak, 63Qiaoxian Mak, 77Gordon Mak, 37Sylvia S Mak, 74
Connected to:
Amy Mak, 46Angelina J Mak, 33Anne N Mak, 39Arthur L Mak, 94Attila Mak, 49Carol S Mak, 65Chen Mak, 76Chenda C Mak, 44Ching Y Mak, 48Cynthia L Mak, 71

Chit Mak Phones & Addresses

  • 577 Rough And Ready Rd, San Jose, CA 95133 (510) 623-7342
  • 44201 Ibero Way, Fremont, CA 94539 (510) 623-7342
  • Alameda, CA
  • 44201 Ibero Way, Fremont, CA 94539 (510) 757-4110

Work

Company: Gorana technology Dec 2008 Position: Owner/analog ic design

Education

School / High School: MSEE UC Berkeley- Berkeley, CA 1977

Skills

MS Windows • Cadence AMS/APS/SimVision OPUS/RCX • HSPICE/Pspice • MatLab/Simulink • MathCAD AND UNIX

Languages

Mandarin

Emails

g***a@yahoo.com

Industries

Semiconductors

Resumes

Resumes

Chit Mak Photo 1

Chit Mak

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Location:
Berkeley, CA
Industry:
Semiconductors
Work:
Gorana Technology Jan 1, 2009 - Dec 1, 2014
Self Employed Professonal
Microsoft 2013 - 2014
Contracting Analog Ic Design Engineer
Banpil Photonics, Inc. Jan 1, 2013 - Jun 1, 2013
Contracting Analog Ic Design Engineer
Enphase Energy Mar 1, 2012 - Dec 1, 2012
Contracting Analog Ic Design Engineer
Synaptics Sep 1, 2010 - Jun 1, 2011
Contracting Analog Ic Design and Validation Engineer
Education:
University of California, Berkeley 1975 - 1977
Masters, Master of Science In Electrical Engineering, Design Northeastern University 1970 - 1975
Bachelors, Bachelor of Science, Electrical Engineering, Electrical Engineering and Computer Science, Computer Science
Skills:
Mixed Signal
Digital Signal Processors
Firmware
Power Management
Asic
Adcs
Analog
Semiconductors
Embedded Systems
Matlab
Signal Processing
Low Power Design
Pcb Design
Electronics
Cadence Virtuoso
Pll
Hardware Architecture
Ic
Sensors
Analog Circuit Design
Cmos
Circuit Design
Soc
Eda
Debugging
Languages:
Mandarin
Chit Mak Photo 2

Chit Ah Mak Fremont, CA

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Work:
Gorana Technology

Dec 2008 to Present
Owner/Analog IC Design
Synaptics Inc

Sep 2010 to Jun 2011
Contracting Analog IC Design Engineer
Custom Sensors Technology

Feb 2008 to Dec 2008
Analog Mixed Signal Processing IC Design Engineer
Applied Science and Technology Research Institute

2005 to 2007
Principal Design Engineer in Signal Processing
Intersil Corporation
Milpitas, CA
2004 to 2005
Staff Design Engineer
Exar (Sipex) Corporation
Milpitas, CA
2003 to 2004
Staff Design Engineer
Lightspeed Semiconductor
Sunnyvale, CA
2001 to 2003
Staff Analog Design Engineer
MKNet Corporation
San Jose, CA
1998 to 2001
Staff Analog Design Engineer
Micrel (Synergy) Semi
Santa Clara, CA
1996 to 1998
Member of Technical Staff
IDT (Quality) Semiconductor
Santa Clara, CA
1993 to 1996
Design Engineering Supervisor
Pericom Semiconductor
San Jose, CA
1990 to 1993
Staff Analog Design Engineer
Intel Corp (Chips & Technologies)
San Jose, CA
1986 to 1990
Staff Analog Design Engineer
Silicon Macro System Inc
San Jose, CA
1985 to 1986
Staff Analog Design Engineer
Skills:
MS Windows, Cadence AMS/APS/SimVision OPUS/RCX, HSPICE/Pspice, MatLab/Simulink, MathCAD AND UNIX

Publications

Us Patents

Gain Control Circuit

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US Patent:
7659780, Feb 9, 2010
Filed:
Nov 29, 2007
Appl. No.:
11/947085
Inventors:
Chit Ah Mak - Fremont CA, US
Chun Fai Wong - Hong Kong, HK
Lap Chi Leung - Hong Kong, HK
Xiaofei Kuang - Hong Kong, HK
Jennifer Shuet Yan Ho - Hong Kong, HK
David Kwok Kuen Kwong - Davis CA, US
Assignee:
Hong Kong Applied Science and Technology Research Institute Co., Ltd. - Hong Kong
International Classification:
H03F 3/45
US Classification:
330260, 330 98
Abstract:
A gain control circuit including a resistor with a first terminal and a second terminal; an operational amplifier with an inverting terminal thereof electrically coupled to said first terminal of said resistor; a non-inverting terminal thereof; and an output terminal thereof; an amplifier circuit for transforming the voltage change of said operational amplifier output into a substantially exponential current change; wherein the output of said amplifier circuit is electrically coupled to said inverting terminal of said operational amplifier. The above described gain control circuit is able to perform wide bandwidth input signal buffering with linearity under low voltage and low power conditions. The circuit also offers low output impedances without the need of additional buffers and hence minimizing circuit size and manufacturing costs.

Cmos Tristate Output Buffer With Having Overvoltage Protection And Increased Stability Against Bus Voltage Variations

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US Patent:
58444254, Dec 1, 1998
Filed:
Jul 19, 1996
Appl. No.:
8/694712
Inventors:
Hung T. Nguyen - San Jose CA
Chit Ah Mak - Fremont CA
Steve W. T. Liu - Homebush, AU
Assignee:
Quality Semiconductor, Inc. - Santa Clara CA
International Classification:
H03K 1900
US Classification:
326 58
Abstract:
An overvoltage tolerant CMOS tristate output buffer capable of withstanding tristate overvoltages without reverse currents or latch-up, the output buffer having a stabilized protection circuit for driving the N-well and gate of the P-channel driver transistor to the output pad voltage when the output pad voltage becomes excessive. The stabilized protection circuit includes a hysteresis circuit for controlling switch transistors which bias the N-well. The presence of the hysteresis circuit causes the protection circuit to have an input hysteresis characteristic, thus preventing excessive switching of the N-well biasing transistors when the output pad voltage varies near the output buffer power supply voltage during tristate.
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Chit A Mak from San Jose, CA, age ~73 Get Report