Search

Advait M Mogre

from Sunnyvale, CA
Age ~65
Get Report
Also known as:
Advait Varty Suvarna Mogre, Adviat M Mogre, Advait Moger, Adviat M Morge, Mogre Advait, T E
Phone and address:
1572 Mallard Way, Sunnyvale, CA 94087
(408) 245-0807
Related to:
Aparna Kulkarni, 35
Connected to:
Jack L Mogren, 65Katherine Mogren, 37Leif W Mogren, 36Tiffany R Mogridge, 41Nino M Mogro, 50Gabriela M Mogrovejo, 37Marco Mogrovejo, 44Oscar A Mogrovejo, 47Cyrus Mogtader, 43Linda B Mogue, 76

Advait Mogre Phones & Addresses

  • 1572 Mallard Way, Sunnyvale, CA 94087 (408) 245-0807 (408) 245-1013
  • 585 Saddleback Ter, Fremont, CA 94536 (510) 792-7301 (510) 792-7002
  • 1306 Anthony St, Columbia, MO 65201
  • Santa Clara, CA
  • 1572 Mallard Way, Sunnyvale, CA 94087 (408) 245-1013

Work

Position: Financial Professional

Education

Degree: Graduate or professional degree

Emails

a***[email protected]

Resumes

Resumes

Advait Mogre Photo 1

Principal Scientist

View page
Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Interra Systems
Principal Scientist
Broadcom Jul 2005 - Oct 2012
Senior Principal Scientist
Lsi Logic Corporation Jan 2001 - Jul 2005
Principal Engineer
Lsi Logic Corporation May 1997 - Dec 2000
Engineering Manager I and Ii
Lsi Logic Corporation Jun 1995 - May 1997
Staff Engineer
Education:
University of Missouri - Columbia 1985 - 1990
Doctorates, Doctor of Philosophy, Electrical Engineering, Philosophy Indian Institute of Technology, Bombay 1981 - 1984
Masters, Master of Technology, Engineering Indian Institute of Technology, Bombay 1976 - 1981
Bachelors, Bachelor of Technology, Electronics, Engineering, Communications
Skills:
Algorithms
Vhdl
Ic
Semiconductors
Simulations
Digital Signal Processing
Asic
Analog
C
Signal Processing
Mixed Signal
Vlsi
Digital Communication
Testing
Microprocessors
Matlab
Functional Verification
Integrated Circuits
Algorithms and Asic Architecture
Artificial Intelligence
Circuit Design
Eda
Computer Vision
Advait Mogre Photo 2

Advait Mogre

View page
Location:
San Francisco Bay Area
Industry:
Semiconductors

Publications

Us Patents

System And Method Using Polar Coordinate Representation For Quantization And Distance Metric Determination In An M-Psk Demodulator

View page
US Patent:
6421400, Jul 16, 2002
Filed:
Feb 4, 1999
Appl. No.:
09/244596
Inventors:
Dojun Rhee - San Jose CA
Advait Mogre - Fremont CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H03D 322
US Classification:
375329, 375341, 375265, 714792, 714795
Abstract:
A digital communications receiver is provided with a PSK demodulator and a soft-decision decoder. The PSK demodulator is configured to accept a receive signal and responsively produce quantized baseband signal components which include a quantized radial component R and a quantized angular component. The soft-decision decoder is coupled to the PSK demodulator to receive the quantized baseband signal components and is configured to convert the quantized signal components into decoded information bits. The soft-decision decoder preferably uses a squared Euclidean distance metric calculation for the decoding process. Using polar coordinate quantization provides an improved performance relative to Cartesian coordinate quantization. A new distance metric for TCM decoding is also provided which requires less implementation complexity than a standards Euclidean distance metric calculation, and which suffers no significant performance loss.

Integrated Services Digital Broadcasting Deinterleaver Architecture

View page
US Patent:
6714606, Mar 30, 2004
Filed:
Jan 4, 2000
Appl. No.:
09/477317
Inventors:
Cheng Qian - San Jose CA
Advait Mogre - Fremont CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H04L 2706
US Classification:
375341
Abstract:
An apparatus comprising a memory, a write pointer, a read pointer and a control circuit. The memory may have a plurality of memory locations accessed by a plurality of addresses. The write pointer may be configured to write data to the memory in response to a sequence of write addresses generated in response to a first control signal. The read pointer may be configured to read data from the memory in response to a sequence of read addresses generated in response to a second control signal. The control circuit may be configured to generate (i) the first control signal, and (ii) the second control signal. The order data is read from said memory may comprise a de-interleaved pattern with respect to the order the data is written to the memory.

Method And Apparatus For Decoding M-Psk Turbo Code Using New Approximation Technique

View page
US Patent:
6807238, Oct 19, 2004
Filed:
Feb 1, 2001
Appl. No.:
09/773033
Inventors:
Dojun Rhee - Irvine CA
Advait Mogre - Sunnyvale CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H03D 322
US Classification:
375340, 375329, 375265, 375341, 714786, 714791, 714794, 714796
Abstract:
The method of the present invention decodes a received symbol that represents data bits including message bits and parity-check bits. The method comprises (a) mapping the symbol onto a received signal point in a signal space, the signal point having an in-phase component (I) and a quadrature phase component (Q) in the signal space; (b) computing reliability information for each data bit, the reliability information associated with a distance d ={square root over ((I-I ) +(Q-Q ) )} between the received signal point (I, Q) and a reference constellation point (I , Q ) in the signal space, where i=0, 1,. . . , M-1 (for M an integer), by replacing calculation of (I-I ) +(Q-Q ) with calculation of 2(I ÃI+Q ÃQ); (c) decoding the received symbol using the reliability information and a priori information to produce estimated message bits, the a priori information having a predetermined value in a first decoding; (d) calculating difference between received message bits and the estimated message bits to produce extrinsic information of estimated message bits; and (e) repeating at least once the mapping, computing, decoding and calculating, using the extrinsic information produced in a preceding calculating as the a priori information.

Design And Optimization Methods For Integrated Circuits

View page
US Patent:
6931612, Aug 16, 2005
Filed:
May 15, 2002
Appl. No.:
10/146363
Inventors:
Miodrag Potkonjak - Freemont CA, US
Seapahn Megerian - West Hills CA, US
Advait Mogre - Sunnyvale CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F017/50
US Classification:
716 5, 716 7, 716 8
Abstract:
A method for optimizing an algorithm specified for implementation on an integrated circuit for a specified application. The algorithm is analyzed with respect to its performance, and estimates of implementation area and speed are calculated. Specifically, the degrees of freedom for the algorithm alternations under specific targeted implementation objective functions and constraints are identified. The algorithm solution space is then searched to identify the algorithm structure that is best suited for the specified design goals and constraints. Algorithm parameters which satisfy performance metrics and can be implemented with minimum silicon area are identified.

Multi-Resolution Viterbi Decoding Technique

View page
US Patent:
6948114, Sep 20, 2005
Filed:
Apr 25, 2002
Appl. No.:
10/132360
Inventors:
Miodrag Potkonjak - Fremont CA, US
Seapahn Megerian - West Hills CA, US
Advait Mogre - Sunnyvale CA, US
Dusan Petranovic - Cupertino CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H03M013/03
US Classification:
714792, 714796
Abstract:
A method for decoding an encoded signal. A first step generates a plurality of first precision state metrics for a decoder trellis in response to a plurality of first precision branch metrics. A second step generates a plurality of second precision state metrics for a selected subset of the first precision state metrics in response to a plurality of second precision branch metrics. A third step replaces the selected subset of first precision state metrics with the second precision state metrics. A fourth step stores the first precision state metrics and the second precision state metrics.

System To Efficiently Transmit Two Hdtv Channels Over Satellite Using Turbo Coded 8Psk Modulation For Dss Compliant Receivers

View page
US Patent:
6987543, Jan 17, 2006
Filed:
Nov 30, 2000
Appl. No.:
09/726819
Inventors:
Advait M. Mogre - Sunnyvale CA, US
Dojun Rhee - Irvine CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H04N 5/40
H04L 7/04
US Classification:
348608, 375262
Abstract:
A channel encoding system and a channel decoding system for use in transmitting multiple high definition television programs in a single satellite channel. The channel encoding system may comprise a frame formatter that may be configured to format a transport stream to produce a block stream. An error correction encoder may be configured to encode the block stream to produce an error protected block stream. An interleave module may be configured to interleave the error protected block stream to produce a data stream. A turbo encoder may be configured to encode the data stream to produce an encoded stream. A bit-to-symbol mapper may be configured to map the encoded stream to produce a symbol stream capable of at least eight different symbols. Finally, a modulator may be configured to modulate the symbol stream.

Metacores: Design And Optimization Techniques

View page
US Patent:
7017126, Mar 21, 2006
Filed:
Nov 26, 2002
Appl. No.:
10/304289
Inventors:
Miodrag Potkoniak - Fremont CA, US
Seapahn Megerian - West Hills CA, US
Advait Mogre - Sunnyvale CA, US
Dusan Petranovic - Cupertino CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F 17/50
H03M 13/03
US Classification:
716 1, 716 4, 714792, 714795, 714799
Abstract:
A method for developing a circuit is disclosed. The method generally comprises the steps of (A) generating a solution space having a dimension for each of a plurality of parameters for the circuit, (B) evaluating a plurality of instances of the circuit in the solution space through a software simulation, (C) evaluating the instances through a hardware simulation, and (D) updating the instances in response to the software simulation and the hardware simulation to approach an optimum instance of the instances for the circuit.

Method And Apparatus For Extracting Information From Burst Cutting Area Of Recording Medium

View page
US Patent:
7414943, Aug 19, 2008
Filed:
Jan 6, 2005
Appl. No.:
11/031208
Inventors:
Eric MacDonald - Los Gatos CA, US
Advait Mogre - Sunnyvale CA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
G11B 20/10
US Classification:
369 5925, 36912407
Abstract:
A method and apparatus extract information from a burst cutting area (BCA) of a recording medium. The BCA extraction includes (a) receiving a signal from the recording medium, the signal including BCA data read from the BCA, the BCA data being represented by channel symbols, (b) analog-to-digital (A/D) sampling the signal to generate input data, (c) identifying a BCA region within the input data, the BCA region corresponding to the BCA data, (d) determining an average channel symbol width of the BCA data, the average channel symbol width corresponding to an average number of A/D samples per channel symbol in the BCA data, (e) increasing a signal-to-noise ratio (SNR) of the BCA data using the average channel symbol width, (f) generating a channel pattern data from the BCA data using a selected threshold value, and (g) generating a channel symbol data from the channel pattern data using the average channel symbol width.
Control profile
Advait M Mogre from Sunnyvale, CA, age ~65 Get Report