Abiola Abimbola A Awujoola

7166492, Jan 23, 2007

Nov 14, 2003

10/713951

Abiola Awujoola - Union City CA, US
Clifford R. Fishley - San Jose CA, US

LSI Logic Corporation - Milpitas CA

H01L 21/00
H01L 23/02
G06F 17/50

438106, 257678, 438108, 716 12

A carrier substrate includes an access region placed within the interior of the substrate that facilitates backside access to an integrated circuit die without damaging electrical integrity of the carrier substrate, a ring of die connection pads placed around the access region, and an array of package connection pads positioned around the perimeter of the top surface of the carrier substrate. In one embodiment, the perimeter depth of the array of package connections pads is selected to correspond to the number of electrical traces routable between minimally spaced package connection pads. The basic carrier substrate design is used to create an integrated circuit carrier family with each particular circuit carrier configured to receive a range of integrated circuit sizes and I/O counts such that each circuit carrier overlaps in size range with at least one other circuit carrier.

7750460, Jul 6, 2010

Feb 21, 2008

12/034745

Clifford R. Fishley - San Jose CA, US
Abiola Awujoola - Pleasanton CA, US
Leonard L. Mora - San Jose CA, US

LSI Corporation - Milpitas CA

H01L 23/52

257691, 257692, 257698, 257700, 257774, 257786, 257E23079, 257E23142

A die package generally including (A) ground paths routing a power ground from a ground power set of contact pads in a first conductive layer to a ground ring in a second conductive layer, (B) core paths routing a core voltage from a core power set of contact pads in the first conductive layer to a core ring in the second conductive layer, and (C) input/output voltage paths routing input/output voltages from an input/output power set of contact pads in the first conductive layer to an input/output ring in the second conductive layer, (i) the input/output ring surrounding the core ring, (ii) the ring being configured to power input and output circuits of the die, (iii) the input/output ring being split into ring segments isolated from each other and (iv) at least one particular ring segment having a length of less than a single connector pitch.

7804167, Sep 28, 2010

Dec 1, 2006

11/565701

Clifford Fishley - San Jose CA, US
Abiola Awujoola - Pleasanton CA, US
Leonard Mora - San Jose CA, US
Amar Amin - Milpitas CA, US
Maurice Othieno - Union City CA, US
Chok J. Chia - Cupertino CA, US

LSI Logic Corporation - Milpitas CA

H01L 23/528
H01L 21/768

257691, 257786, 257692, 257784, 257782, 257E23079, 257E23153, 257E21575, 438666, 438612, 438622

An integrated circuit package includes a package substrate, a die attach pad formed on the package substrate for securing a die to the package substrate, a ground bonding ring formed on the package substrate for attaching core and I/O ground bond wires between the die and the package substrate, and a first plurality of bond fingers formed immediately adjacent to the ground bonding ring for attaching a first set of I/O signal bond wires between the package substrate and the die.

20030221178, Nov 27, 2003

May 24, 2002

10/155260

Leonard Mora - San Jose CA, US
Abiola Awujoola - Union City CA, US
Jeffrey Hall - Kamakura-shi, JP

G06F017/50

716/012000, 716/014000

A substrate of the type for receiving an integrated circuit and a mold cover. The mold cover covers a first portion of the substrate and leaves a second portion of the substrate exposed with a boundary edge between the first portion of the substrate and a second portion of the substrate. The substrate has electrically conductive traces and electrically conductive vias on an upper layer adjacent the mold cover. The electrically conductive traces do not cross the boundary edge on the upper layer of the substrate.

20050104164, May 19, 2005

Nov 14, 2003

10/713952

Abiola Awujoola - Union City CA, US
Clifford Fishley - San Jose CA, US

LSI LOGIC CORPORATION - Milpitas CA

H01L023/552

257659000

A package shell that is electrically and thermally conductive is placed over an integrated circuit die and associated wire-bond connections to electromagnetically shield the resulting integrated circuit package. The package shell is attached to the top surface of a substrate bearing the integrated circuit die and is electrically connected to a grounding path. The package shell may be filled with a thermally conductive filler in order to increase the heat dissipation and EMI shielding of the resulting integrated circuit package.

20120126387, May 24, 2012

Nov 24, 2010

12/953669

Clifford R. Fishley - San Jose CA, US
Abiola Awujoola - Pleasanton CA, US

LSI Corporation - Milpitas CA

H01L 23/367
H01L 21/50

257690, 438122, 257E23103, 257E21499

An electronic device includes an integrated circuit (IC) die attached to a substrate, and electrical conductors connecting the IC die to the substrate. The electronic device also includes a heat spreader located over the IC die and having a concaved portion located over the IC die along with a lateral portion extending from the concaved portion. The lateral portion has a surface area greater than a surface area of the concaved portion. A support member is further included that extends from the lateral portion to and contacts the substrate. An encapsulant covers the support member leaving the lateral and concaved portions exposed on outer sides thereof. In another aspect, a method of manufacturing an electronic device is also included.

20130161804, Jun 27, 2013

Dec 21, 2011

13/333294

Clifford R. Fishley - San Jose CA, US
John J. Krantz - Northampton PA, US
Abiola Awujoola - Pleasanton CA, US
Allen S. Lim - San Jose CA, US
Stephen M. King - Hamburg PA, US
Lawrence W. Golick - Nazareth PA, US

H01L 23/495
H01L 21/00

257676, 29827, 257E23052

Provided, in one embodiment, is an integrated circuit (IC) leadframe. In one example, the leadframe includes a paddle, wherein the paddle has a surface configured to accept an IC chip and has at least one edge. In this example, the leadframe may further include a plurality of lead fingers having ends extending toward the at least one edge, wherein the ends of ones of adjacent lead fingers are staggered proximate and distal the at least one edge.

20130161805, Jun 27, 2013

Dec 21, 2011

13/333604

Clifford R. Fishley - San Jose CA, US
John J. Krantz - Northampton PA, US
Abiola Awujoola - Pleasanton CA, US
Allen S. Lim - San Jose CA, US
Stephen M. King - Hamburg PA, US
Lawrence W. Golick - Nazareth PA, US
Ashley Rebelo - Allentown PA, US

LSI Corporation - Milpitas CA

H01L 23/495
H05K 3/30

257676, 29832, 257E23031

Provided, in one embodiment, is an integrated circuit (IC) leadframe. In one example, the leadframe includes a paddle, wherein the paddle has a surface configured to accept an IC chip and has at least one edge, the at least one edge having one or more slots located therein. In this example, the leadframe may further include a plurality of lead fingers having ends extending toward the at least one edge, wherein the ends of ones of pairs of adjacent lead fingers extend into corresponding slots in the paddle.