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Abhishek Raj Appu

from El Dorado Hills, CA
Age ~46
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Also known as:
Abhishek R Appu, Abhishek A Appu, Raj Appu Abhishek, Appu Abhishek
Related to:
Appu AbhishekRaghavan DevarajanDebajani Majhi, 44Ashok AppuAbha Appu, 50
Connected to:
Carlo J Appugliese, 86Frank D Appugliese, 104Hilda D Appuhn, 72Annette R Appuliese, 63Christian G Appy, 69Anne M Apra, 61Alex M Aprahamian, 59Faustina O Apraku, 32Kwame A Apraku, 35Albert J Aprea, 76

Abhishek Appu Phones & Addresses

  • El Dorado Hills, CA
  • Vancouver, WA
  • Litchfield Park, AZ
  • Phoenix, AZ
  • Austin, TX
  • Santa Clara, CA
  • Milpitas, CA
  • Sunnyvale, CA
  • Fremont, CA
  • Sacramento, CA
  • Orangevale, CA

Resumes

Resumes

Abhishek Appu Photo 1

Principal Engineer

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Location:
Sacramento, CA
Industry:
Computer Hardware
Work:
Intel Corporation
Principal Engineer
Intel Corporation Jan 2014 - Dec 2017
Senior Staff Engineer
Intel Corporation Jan 2011 - Dec 2013
Staff Engineer
Intel Corporation Dec 2008 - Dec 2010
Senior Hardware Engineer
Nvidia Dec 2007 - Dec 2008
Senior Asic Design Engineer
Education:
Indian Institute of Technology, Kanpur 1995 - 1999
St Joseph High School
Skills:
Asic
Rtl Design
Systemverilog
Vlsi
Debugging
Verilog
Semiconductors
Static Timing Analysis
Ic
Soc
Perl
Fpga
Abhishek Appu Photo 2

Abhishek Appu

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Publications

Us Patents

Barrier State Save And Restore For Preemption In A Graphics Environment

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US Patent:
20220413899, Dec 29, 2022
Filed:
Jun 25, 2021
Appl. No.:
17/358882
Inventors:
- Santa Clara CA, US
James Valerio - North Plains OR, US
Joydeep Ray - Folsom CA, US
Abhishek R. Appu - El Dorado Hills CA, US
Alan Curtis - El Dorado Hills CA, US
Prathamesh Raghunath Shinde - Folsom CA, US
Brandon Fliflet - El Dorado Hills CA, US
Ben J. Ashbaugh - Folsom CA, US
John Wiegert - Aloha OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 9/48
G06F 9/38
G06T 1/20
Abstract:
An apparatus to facilitate barrier state save and restore for preemption in a graphics environment is disclosed. The apparatus includes processing resources to execute a plurality of execution threads that are comprised in a thread group (TG) and mid-thread preemption barrier save and restore hardware circuitry to: initiate an exception handling routine in response to a mid-thread preemption event, the exception handling routine to cause a barrier signaling event to be issued; receive indication of a valid designated thread status for a thread of a thread group (TG) in response to the barrier signaling event; and in response to receiving the indication of the valid designated thread status for the thread of the TG, cause, by the thread of the TG having the valid designated thread status, a barrier save routine and a barrier restore routine to be initiated for named barriers of the TG.

Typed Unordered Access View Overloading On Pixel Pipeline

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US Patent:
20220414813, Dec 29, 2022
Filed:
Jun 23, 2021
Appl. No.:
17/356043
Inventors:
- Santa Clara CA, US
Prasoonkumar Surti - Folsom CA, US
Abhishek R. Appu - El Dorado Hills CA, US
International Classification:
G06T 1/20
G06T 1/60
Abstract:
Methods, systems and apparatuses provide for graphics processor technology that routes untyped unordered access view (UAV) messages to a next level memory cache, routes typed UAV messages and render target messages to a pixel pipeline, and processes, via the pixel pipeline, the typed UAV messages. The technology can also provide for the pixel pipeline to perform a format conversion of one or more pixels associated with a typed UAV message based on a surface format of a UAV resource, calculate a memory address for each pixel associated with the typed UAV message, and collect a plurality of fragments from processed typed UAV messages.

Dynamic Allocation Of Cache Based On Instantaneous Bandwidth Consumption At Computing Devices

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US Patent:
20220383447, Dec 1, 2022
Filed:
Jun 7, 2022
Appl. No.:
17/834150
Inventors:
- Santa Clara CA, US
Mohammed Tameem - Mangalore, IN
Altug Koker - El Dorado Hills CA, US
Abhishek R. Appu - El Dorado Hills CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06T 1/20
G06F 12/02
G06F 12/0875
Abstract:
A mechanism is described for facilitating dynamic cache allocation in computing devices in computing devices. A method of embodiments, as described herein, includes facilitating monitoring one or more bandwidth consumptions of one or more clients accessing a cache associated with a processor; computing one or more bandwidth requirements of the one or more clients based on the one or more bandwidth consumptions; and allocating one or more portions of the cache to the one or more clients in accordance with the one or more bandwidth requirements.

Instructions And Logic To Perform Floating Point And Integer Operations For Machine Learning

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US Patent:
20220357945, Nov 10, 2022
Filed:
Jun 7, 2022
Appl. No.:
17/834482
Inventors:
- Santa Clara CA, US
Mark A. Anders - Hillsboro OR, US
Sanu K. Mathew - Hillsboro OR, US
Anbang Yao - Beijing, CN
Joydeep Ray - Folsom CA, US
Ping T. Tang - Edison NJ, US
Michael S. Strickland - Sunnyvale CA, US
Xiaoming Chen - Shanghai, CN
Tatiana Shpeisman - Menlo Park CA, US
Abhishek R. Appu - El Dorado Hills CA, US
Altug Koker - El Dorado Hills CA, US
Kamal Sinha - Rancho Cordova CA, US
Balaji Vembu - Folsom CA, US
Nicolas C. Galoppo Von Borries - Portland OR, US
Eriko Nurvitadhi - Hillsboro OR, US
Rajkishore Barik - Santa Clara CA, US
Tsung-Han Lin - Campbell CA, US
Vasanth Ranganathan - El Dorado Hills CA, US
Sanjeev Jahagirdar - Folsom CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 9/30
G09G 5/393
G06F 9/38
G06F 7/483
G06F 7/544
G06N 3/04
G06N 3/063
G06N 3/08
Abstract:
One embodiment provides a graphics processor comprising a memory controller and a graphics processing resource coupled with the memory controller. The graphics processing resource includes circuitry configured to execute an instruction to perform a matrix operation on first input including weight data and second input including input activation data, generate intermediate data based on a result of the matrix operation, quantize the intermediate data to a floating-point format determined based on a statistical distribution of first output data, and output, as second output data, quantized intermediate data in a determined floating-point format.

Efficient Thread Group Scheduling

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US Patent:
20220350651, Nov 3, 2022
Filed:
May 17, 2022
Appl. No.:
17/746201
Inventors:
- Santa Clara CA, US
Abhishek R. Appu - El Dorado Hills CA, US
Altug Koker - El Dorado Hills CA, US
Kamal Sinha - Rancho Cordova CA, US
Balaji Vembu - Folsom CA, US
Rajkishore Barik - Santa Clara CA, US
Eriko Nurvitadhi - Hillsboro OR, US
Nicolas Galoppo Von Borries - Portland OR, US
Tsung-Han Lin - Campbell CA, US
Sanjeev Jahagirdar - Folsom CA, US
Vasanth Ranganathan - El Dorado Hills CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 9/48
G06T 1/20
Abstract:
A mechanism is described for facilitating intelligent thread scheduling at autonomous machines. A method of embodiments, as described herein, includes detecting dependency information relating to a plurality of threads corresponding to a plurality of workloads associated with tasks relating to a processor including a graphics processor. The method may further include generating a tree of thread groups based on the dependency information, where each thread group includes multiple threads, and scheduling one or more of the thread groups associated a similar dependency to avoid dependency conflicts.

Systems And Methods For Cache Optimization

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US Patent:
20220350751, Nov 3, 2022
Filed:
Jul 12, 2022
Appl. No.:
17/862739
Inventors:
- Santa Clara CA, US
Joydeep Ray - Folsom CA, US
Abhishek Appu - El Dorado Hills CA, US
Aravindh Anantaraman - Folsom CA, US
Valentin Andrei - San Jose CA, US
Durgaprasad Bilagi - Folsom CA, US
Varghese George - Folsom CA, US
Brent Insko - Portland OR, US
Sanjeev Jahagirdar - Folsom CA, US
Scott Janus - Loomis CA, US
Pattabhiraman K - Bangalore, IN
SungYe Kim - Folsom CA, US
Subramaniam Maiyuran - Gold River CA, US
Vasanth Ranganathan - El Dorado Hills CA, US
Lakshminarayanan Striramassarma - Folsom CA, US
Xinmin Tian - Union City CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/123
G06F 12/0875
G06F 12/0891
G06T 1/60
Abstract:
Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received. In one embodiment, the cache memory configured to be partitioned into multiple cache regions, wherein the multiple cache regions include a first cache region having a cache eviction policy with a configurable level of data persistence.

Page Faulting And Selective Preemption

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US Patent:
20220351325, Nov 3, 2022
Filed:
May 20, 2022
Appl. No.:
17/749266
Inventors:
- Santa Clara CA, US
Ingo Wald - Salt Lake City UT, US
David Puffer - Tempe AZ, US
Subramaniam M. Maiyuran - Gold River CA, US
Prasoonkumar Surti - Folsom CA, US
Balaji Vembu - Folsom CA, US
Murali Ramadoss - Folsom CA, US
Abhishek R. Appu - El Dorado Hills CA, US
Joydeep Ray - Folsom CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06T 1/20
G06F 9/46
G06F 9/48
G06F 9/30
G06F 9/38
Abstract:
One embodiment provides a parallel processor comprising a memory interface and a processing array coupled with the memory interface. The processing array is configured to address memory accessed via the memory interface via a virtual address mapping and includes circuitry to resolve a page fault for the virtual address mapping, wherein each of the multiple compute blocks is separately preemptable.

Cache Optimization For Graphics Systems

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US Patent:
20220334977, Oct 20, 2022
Filed:
Apr 7, 2022
Appl. No.:
17/715734
Inventors:
- Santa Clara CA, US
Balaji Vembu - Folsom CA, US
Joydeep Ray - Folsom CA, US
Abhishek R. Appu - El Dorado Hills CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/0895
G06F 12/126
G06F 12/02
G06T 1/60
Abstract:
A mechanism is described for facilitating optimization of cache associated with graphics processors at computing devices. A method of embodiments, as described herein, includes introducing coloring bits to contents of a cache associated with a processor including a graphics processor, wherein the coloring bits to represent a signal identifying one or more caches available for use, while avoiding explicit invalidations and flushes.
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Abhishek Raj Appu from El Dorado Hills, CA, age ~46 Get Report