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Abhijit M Abhyankar

from Sunnyvale, CA
Age ~54

Abhijit Abhyankar Phones & Addresses

  • 874 Pippin Dr, Sunnyvale, CA 94087 (408) 455-6420
  • 1158 Bennington Dr, Sunnyvale, CA 94087 (408) 245-4756
  • 1063 Morse Ave, Sunnyvale, CA 94089 (408) 541-1260
  • Belmont, CA
  • Slc, UT
  • Santa Clara, CA
  • Mountain View, CA
  • New York, NY

Resumes

Resumes

Abhijit Abhyankar Photo 1

Vice President Silicon Engineering

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Location:
874 Pippin Dr, Sunnyvale, CA 94087
Industry:
Semiconductors
Work:
Flex Logix Technologies, Inc.
Vice President Silicon Engineering

Rambus Jan 2011 - Feb 2012
Technical Director

Rambus Jul 2008 - Jan 2011
Senior Engineering Director and India Development Center Site Manager

Rambus Jan 2007 - Jun 2008
Engineering Director

Rambus Jan 2005 - Jan 2007
Senior Engineering Manager
Education:
Stanford University 1992 - 1993
Masters, Master of Science In Electrical Engineering, Vlsi Design
University of Utah 1987 - 1992
Bachelors, Bachelor of Science In Electrical Engineering, Electrical Engineering
San Jose State University
Master of Business Administration, Masters, Business Administration, Management, Business Administration and Management
Skills:
Asic
Semiconductors
Soc
Patents
Ip
Product Development
Vlsi
Mixed Signal
Rtl Design
Semiconductor Industry
Ic
Simulations
Analog
Debugging
Verilog
Processors
Eda
Licensing
Serdes
Abhijit Abhyankar Photo 2

Abhijit Abhyankar

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Abhijit Abhyankar Photo 3

Abhijit Abhyankar

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Location:
San Francisco Bay Area
Industry:
Semiconductors

Publications

Us Patents

Apparatus And Method For Maximizing Information Transfers Over Limited Interconnect Resources

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US Patent:
6347354, Feb 12, 2002
Filed:
Oct 9, 1998
Appl. No.:
09/169748
Inventors:
Abhijit M. Abhyankar - Sunnyvale CA
Frederick A. Ware - Los Altos Hills CA
Donald C. Stark - Los Altos CA
Craig E. Hampel - San Jose CA
Paul G. Davis - San Jose CA
Assignee:
Rambus Incorporated - Mountain View CA
International Classification:
G06F 1200
US Classification:
711 5, 711167, 711217, 711220
Abstract:
The present invention provides various techniques for optimized transfer of information in electronic systems involving memory devices to improve data bandwidth. The invention offers solutions to the problem of packing all of the required information including data, control and address information over a limited number of interconnect lines in an optimized fashion. In one embodiment, the present invention combines different control information, such as row address and bank address information into a unified address field wherein one or more bits can be shared. By sharing bits across various address fields, the present invention conserves bandwidth that is required by the control signals. In another embodiment, the present invention provides various schemes for defining and constructing packets of information that maximize the amount of information carried by a given packet across a limited number of interconnect lines.

High Speed Memory System Capable Of Selectively Operating In Non-Chip-Kill And Chip-Kill Modes

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US Patent:
6370668, Apr 9, 2002
Filed:
Sep 14, 1999
Appl. No.:
09/395160
Inventors:
Frederick Abbott Ware - Los Altos Hills CA
Craig E. Hampel - San Jose CA
Richard M. Barth - Palo Alto CA
Don Stark - Los Altos CA
Abhijit Mukund Abhyankar - Sunnyvale CA
Catherine Yuhjung Chen - Milpitas CA
Thomas J. Sheffler - San Francisc CA
Ely K. Tsern - Los Altos CA
Steven Cameron Woo - Saratoga CA
Assignee:
Rambus INC - Los Altos CA
International Classification:
G11C 2900
US Classification:
714763, 714710
Abstract:
The present invention provides a high data bandwidth memory system capable of operating in non-chip-kill and chip-kill modes. In chip-kill mode, cycle multiplexing, bit multiplexing, and time and space multiplexing are used to read/write data and syndrome across a group of memory devices. Current command packet formats are adapted to communicate with the group of memory devices in chip-kill mode.

Memory Device And System Including A Low Power Interface

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US Patent:
6378018, Apr 23, 2002
Filed:
Oct 9, 1998
Appl. No.:
09/169506
Inventors:
Ely K. Tsern - Los Altos CA
Thomas J. Holman - Portland OR
Richard M. Barth - Palo Alto CA
Andrew V. Anderson - Portland OR
Paul G. Davis - San Jose CA
Craig E. Hampel - San Jose CA
Donald C. Stark - Los Altos CA
Abhijit M. Abhyankar - Sunnyvale CA
Assignee:
Intel Corporation - Santa Clara CA
Rambus, Inc. - Los Altos CA
International Classification:
G06F 1300
US Classification:
710129, 710128, 713323, 713320, 711105, 711 5
Abstract:
A memory system includes an interconnect structure with a high speed channel and a low speed channel. A memory device with interface circuitry is coupled to the interconnect structure. The interface circuitry includes a high power interface for coupling to the high speed channel and a low power interface for coupling to the low speed channel. The memory device is operative in a low power mode and a high power mode. A memory controller is coupled to the high speed channel and the low speed channel of the interconnect structure. The memory controller is configured to transmit control information over the low speed channel to set the power mode of the memory device. The memory device is operative in a low power mode during which high power receiver circuits are turned off. The memory device is also operative in a nap mode during which an internal clock compensation circuit is left on to preserve phase information. The memory system may include multiple memory devices coupled to a daisy chained lead of the interconnect structure.

High Performance Cost Optimized Memory

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US Patent:
6401167, Jun 4, 2002
Filed:
Oct 9, 1998
Appl. No.:
09/169206
Inventors:
Richard M. Barth - Palo Alto CA
Frederick A. Ware - Los Altos Hills CA
Donald C. Stark - Los Altos CA
Craig E. Hampel - San Jose CA
Paul G. Davis - San Jose CA
Abhijit M. Abhyankar - Sunnyvale CA
James A. Gasbarro - Mountain View CA
David Nguyen - San Jose CA
Assignee:
Rambus Incorporated - Los Altos CA
International Classification:
G06F 1200
US Classification:
711106, 36523003, 365233, 365222, 711154
Abstract:
A memory device includes an interconnect with mask pins and a memory core for storing data. A memory interface circuit is connected between the interconnect and the memory core. The memory interface circuit selectively processes write mask data from the mask pins or precharge instruction signals from the mask pins.

Method And Apparatus For Fail-Safe Resynchronization With Minimum Latency

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US Patent:
6473439, Oct 29, 2002
Filed:
Oct 9, 1998
Appl. No.:
09/169372
Inventors:
Jared LeVan Zerbe - Palo Alto CA
Michael Tak-kei Ching - Sunnyvale CA
Abhijit M. Abhyankar - Sunnyvale CA
Richard M. Barth - Palo Alto CA
Andy Peng-Pui Chan - San Jose CA
Paul G. Davis - San Jose CA
William F. Stonecypher - San Jose CA
Assignee:
Rambus Incorporated - Los Altos CA
International Classification:
H04J 306
US Classification:
370503, 713400, 713600
Abstract:
A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.

Memory System With Channel Multiplexing Of Multiple Memory Devices

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US Patent:
6708248, Mar 16, 2004
Filed:
Dec 8, 1999
Appl. No.:
09/457155
Inventors:
Frederick Abbott Ware - Los Altos Hills CA
Craig E. Hampel - San Jose CA
Richard M. Barth - Palo Alto CA
Donald C. Stark - Los Altos CA
Abhijit Mukund Abhyankar - Sunnyvale CA
Catherine Yuhjung Chen - Milpitas CA
Thomas J. Sheffler - San Francisco CA
Ely K. Tsern - Los Altos CA
Steven Cameron Woo - Saratoga CA
Assignee:
Rambus Inc. - Los Altos CA
International Classification:
G06F 1200
US Classification:
711104, 711147, 711154, 711167, 710 28, 710 33
Abstract:
A high-speed memory system is disclosed in which a single command effects control over either a single memory device or a plurality of memory devices depending on a present mode of operation. Such control may effect data transfer between the one or more memory devices and a memory controller, as well as operating state transitions or power mode transitions for the memory devices. Similarly, various configurations of relatively low bandwidth memory devices respond as a selectively controllable group to transmit or receive high bandwidth data.

Apparatus And Method For Maximizing Information Transfers Over Limited Interconnect Resources

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US Patent:
6757789, Jun 29, 2004
Filed:
Jan 30, 2002
Appl. No.:
10/066488
Inventors:
Abhijit M. Abhyankar - Sunnyvale CA
Frederick A. Ware - Los Altos Hills CA
Donald C. Stark - Los Altos CA
Craig E. Hampel - San Jose CA
Paul G. Davis - San Jose CA
Assignee:
Rambus, Inc. - Los Altos CA
International Classification:
G00F 1200
US Classification:
711145, 711154, 711220, 711133, 712224, 712229
Abstract:
The present invention provides various techniques for optimized transfer of information in electronic systems involving memory devices to improve data bandwidth. The invention offers solutions to the problem of packing all of the required information including data, control and address information over a limited number of interconnect lines in an optimized fashion. In one embodiment, the present invention combines different control information, such as row address and bank address information into a unified address field wherein one or more bits can be shared. By sharing bits across various address fields, the present invention conserves bandwidth that is required by the control signals. In another embodiment, the present invention provides various schemes for defining and constructing packets of information that maximize the amount of information carried by a given packet across a limited number of interconnect lines.

Memory Module With Offset Data Lines And Bit Line Swizzle Configuration

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US Patent:
6839266, Jan 4, 2005
Filed:
Mar 20, 2002
Appl. No.:
10/101243
Inventors:
Frederick Abbott Ware - Los Altos Hills CA, US
Craig E. Hampel - San Jose CA, US
Richard M. Barth - Palo Alto CA, US
Don Stark - Los Altos CA, US
Abhijit Mukund Abhyankar - Sunnyvale CA, US
Catherine Yuhjung Chen - Milpitas CA, US
Thomas J. Sheffler - San Francisco CA, US
Ely K. Tsern - Los Altos CA, US
Steven Cameron Woo - Saratoga CA, US
Assignee:
Rambus Inc. - Los Altos CA
International Classification:
G06F 1340
US Classification:
365 69, 36518511, 36518908, 365231, 365 70, 711 5
Abstract:
A memory module includes an array of N memory devices, each memory device having M data pins, where N is greater than M, and M and N are positive integers; and N bit lines traversing the array of N memory devices, such that each one of the N bit lines is connected to M of the N memory devices.
Abhijit M Abhyankar from Sunnyvale, CA, age ~54 Get Report