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Abbas Te Morshed

from Los Altos, CA
Age ~63
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Also known as:
Abbas L Morshed
Phone and address:
1315 Oak Ave, Los Altos, CA 94024
(650) 969-4621
Related to:
Marci L Corwin, 59Lane G Burns, 28Justin S Burns, 60Jennifer Hill, 35Lifelong O TherapyJosephine Harter, 64Michael Morshed, 63
Connected to:
Abu M Morshed, 66Alam Morshed, 46Somayeh Morshedi, 42Cherine Y Morsi, 43Sherif K Morsi, 38Michael Morsilli, 50Mary E Morsink, 97Warren M Morski, 66Melissa Morsli, 53Amy F Morsman, 52

Abbas Morshed Phones & Addresses

  • 1315 Oak Ave, Los Altos, CA 94024 (650) 969-4621
  • Los Altos Hills, CA
  • Fremont, CA
  • Foster City, CA
  • San Carlos, CA
  • Mountain View, CA
  • 1315 Oak Ave, Los Altos, CA 94024 (650) 823-9739

Work

Company: Xilinx limited Feb 2015 Position: Senior asic design engineer

Education

Degree: Bachelors School / High School: The University of Manchester Specialities: Computer Engineering

Skills

Ethernet • Fpga • Asic • Embedded Systems • Debugging • Verilog • Storage • System Architecture • Tcp/Ip • Snmp • Ip • Solaris • Cloud Computing • Unix • Data Center

Emails

a***o@aol.com

Industries

Information Technology And Services

Resumes

Resumes

Abbas Morshed Photo 1

Senior Asic Design Engineer

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Location:
San Francisco, CA
Industry:
Information Technology And Services
Work:
Xilinx Limited
Senior Asic Design Engineer
Saratoga Speed, Inc. Sep 2013 - Jan 2015
Mts
Oracle Feb 2010 - Sep 2013
Principle Hw Engineer
Sun Microsystems Jun 2008 - Feb 2010
Mts
Xsigo Systems 2005 - 2007
Consultant
Education:
The University of Manchester
Bachelors, Computer Engineering
Skills:
Ethernet
Fpga
Asic
Embedded Systems
Debugging
Verilog
Storage
System Architecture
Tcp/Ip
Snmp
Ip
Solaris
Cloud Computing
Unix
Data Center

Publications

Us Patents

Input/Output Device Including A Mechanism For Accelerated Error Handling In Multiple Processor And Multi-Function Systems

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US Patent:
8286027, Oct 9, 2012
Filed:
May 25, 2010
Appl. No.:
12/787001
Inventors:
John E. Watkins - Sunnyvale CA, US
Elisa Rodrigues - Union City CA, US
Abbas Morshed - Los Altos CA, US
Assignee:
Oracle International Corporation - Redwood City CA
International Classification:
G06F 11/00
US Classification:
714 51, 714 511, 714 43, 714 49, 714 56
Abstract:
An I/O device includes a host interface that may receive and process transaction packets sent by a number of processing units, with each processing unit corresponding to a respective root complex. The host interface includes an error handling unit having error logic implemented in hardware that may determine, as each packet is received, whether each transaction packet has an error and to store information corresponding to any detected errors. The error handling unit may include an error processor that may be configured to execute error processing instructions to determine any error processing operations based upon the information. The error processor may also generate and send one or more instruction operations, each corresponding to a particular error processing operation. The error handling unit may also include an error processing unit that may execute the one or more instruction operations to perform the particular error processing operations.

Method For Performing Protocol Translation In A Network Switch

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US Patent:
20110228782, Sep 22, 2011
Filed:
May 27, 2011
Appl. No.:
13/117768
Inventors:
Fong Liaw - Cupertino CA, US
Jan Medved - Pleasanton CA, US
Abbas Morshed - Los Altos CA, US
Yijun Xiong - Plano TX, US
John Z. Yu - Santa Clara CA, US
International Classification:
H04L 12/56
H04J 3/16
US Classification:
370392, 370466
Abstract:
A system and method are disclosed for processing a packet. Processing the packet comprises receiving the packet; translating the packet from a first protocol-specific format to a canonical packet format; translating the packet from the canonical packet format to a second protocol-specific format; and forwarding the packet.

Method For Performing Protocol Translation In A Network Switch

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US Patent:
7970009, Jun 28, 2011
Filed:
Aug 21, 2003
Appl. No.:
10/646340
Inventors:
Fong Liaw - Cupertino CA, US
Jan Medved - Pleasanton CA, US
Abbas Morshed - Los Altos CA, US
Yijun Xiong - Plano TX, US
John Z. Yu - Santa Clara CA, US
Assignee:
Brixham Solutions Ltd. - Tortola
International Classification:
H04J 3/22
US Classification:
370466, 370469
Abstract:
A system and method are disclosed for processing a packet. Processing the packet comprises receiving the packet; translating the packet from a first protocol-specific format to a canonical packet format; translating the packet from the canonical packet format to a second protocol-specific format; and forwarding the packet.

Localized Noc Switching Interconnect For High Bandwidth Interfaces

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US Patent:
20220337923, Oct 20, 2022
Filed:
Apr 16, 2021
Appl. No.:
17/232207
Inventors:
- San Jose CA, US
Sagheer AHMAD - Cupertino CA, US
Ygal ARBEL - Morgan Hill CA, US
Abbas MORSHED - Los Altos CA, US
Eun Mi KIM - San Jose CA, US
International Classification:
H04Q 3/00
G06F 13/40
G06F 13/16
Abstract:
Embodiments herein describe an integrated circuit that includes a NoC with at least two levels of switching: a sparse network and a non-blocking network. In one embodiment, the non-blocking network is a localized interconnect that provides an interface between the sparse network in the NoC and a memory system that requires additional bandwidth such as HBM2/3 or DDR5. Hardware elements connected to the NoC that do not need the additional benefits provided by the non-blocking network can connect solely to the sparse network. In this manner, the NoC provides a sparse network (which has a lower density of switching elements) for providing communication between lower bandwidth hardware elements and a localized non-blocking network for facilitating communication between the sparse network and higher bandwidth hardware elements.

Dynamically Allocated Buffer Pooling

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US Patent:
20230036531, Feb 2, 2023
Filed:
Jul 29, 2021
Appl. No.:
17/389272
Inventors:
- San Jose CA, US
Shishir KUMAR - Hyderabad, IN
Sagheer AHMAD - Cupertino CA, US
Abbas MORSHED - Los Altos CA, US
Aman GUPTA - Sunnyvale CA, US
Assignee:
XILINX, INC. - San Jose CA
International Classification:
G06F 3/06
Abstract:
Some examples described herein provide a buffer memory pool circuitry that comprises a plurality of buffer memory circuits that store an entry identifier, a payload portion, and a next-entry pointer. The buffer memory pool circuitry further comprises a processor configured to identify an allocation request for a first virtual channel associated with a sequence of buffer memory circuits and comprising a start pointer identifying an initial buffer memory circuit. The processor is further configured to program the first virtual channel circuit based on setting the start pointer for the first virtual channel circuit to be equal to the entry identifier of the initial buffer memory circuit. The processor is also configured to monitor usage. A length of the sequence of buffer memory circuits of the first virtual channel circuit is defined by a start pointer for a second virtual channel circuit subsequent to the first virtual channel circuit.

Method For Performing Protocol Translation In A Network Switch

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US Patent:
20150365356, Dec 17, 2015
Filed:
Aug 25, 2015
Appl. No.:
14/835517
Inventors:
- Tortola, VG
Jan Medved - Pleasanton CA, US
Abbas Morshed - Los Altos CA, US
Yijun Xiong - Plano TX, US
John Z. Yu - Santa Clara CA, US
International Classification:
H04L 12/935
H04L 12/931
Abstract:
A system and method are disclosed for processing a packet. Processing the packet comprises receiving the packet; translating the packet from a first protocol-specific format to a canonical packet format; translating the packet from the canonical packet format to a second protocol-specific format; and forwarding the packet.
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Abbas Te Morshed from Los Altos, CA, age ~63 Get Report