Yu E Liao

7904795, Mar 8, 2011

Mar 3, 2009

12/397237

Yu Liao - Longmont CO, US
William G. Bliss - Thornton CO, US
Engling Yeo - San Diego CA, US

STMicroelectronics, Inc. - Coppell TX

H03M 13/00

714784, 714755, 714766

A decoder for error correction an encoded message, such as one encoded by a turbo encoder, with reduced iterations due to an improved stopping criterion. The decoder includes an error correction loop that iteratively processes a message that is encoded prior to transmittal over a communication channel. The error correction loop generates, such as with a Reed-Solomon decoder, an error location polynomial in each iterative process. A stopping mechanism in the decoder allows an additional iteration of the message decoding based on the error location polynomial, such as by obtaining the degree of the error location polynomial and comparing it to a threshold. In one example, the threshold is the maximum number of symbol errors correctable by the Reed-Solomon code embodied in the decoder. The stopping mechanism allows additional iterations when the stopping criterion (or polynomial degree) is greater than the maximum number of symbol errors correctable by the Reed-Solomon code.

8451158, May 28, 2013

Jun 30, 2011

13/174273

Yu Liao - Longmont CO, US
Hongwei Song - Longmont CO, US

LSI Corporation - Milpitas CA

H03M 1/12

341155, 375276, 342372, 342375, 600437, 600443, 600453, 600457, 600459, 341130, 341160

Various embodiments of the present invention provide systems, apparatuses and methods for performing analog to digital conversion. For example, an analog to digital converter circuit is discussed that includes an analog input, a number of analog to digital converters and a generalized beamformer. The analog to digital converters are operable to receive the analog input and to yield a number of digital streams. Each of the analog to digital converters samples the analog input with different phase offsets. The generalized beamformer is operable to weight and combine the digital streams to yield a digital output.

8604960, Dec 10, 2013

Jul 10, 2012

13/545784

Yu Liao - Longmont CO, US
Nayak Ratnakar Aravind - Allentown PA, US

LSI Corporation - Milpitas CA

H03M 1/12

341155, 375227

Various embodiments of the present invention provide apparatuses and methods for processing data in an oversampled data processing circuit with multiple detectors. For example, an apparatus for processing data is disclosed that includes a first analog to digital converter operable to sample a continuous signal at a first sampling phase to yield a first digital output, a second analog to digital converter operable to sample the continuous signal at a second sampling phase to yield a second digital output, wherein the second sampling phase is different from the first sampling phase, a first detector operable to process the first digital output to yield a first detector output, and a second detector operable to process the second digital output and the first detector output to yield a detected output.

20070113143, May 17, 2007

Oct 25, 2005

11/257868

Yu Liao - Longmont CO, US
William Bliss - Thornton CO, US
Engling Yeo - San Diego CA, US

H03M 13/00

714753000

A decoder for error correction an encoded message, such as one encoded by a turbo encoder, with reduced iterations due to an improved stopping criterion. The decoder includes an error correction loop that iteratively processes a message that is encoded prior to transmittal over a communication channel. The error correction loop generates, such as with a Reed-Solomon decoder, an error location polynomial in each iterative process. A stopping mechanism in the decoder allows an additional iteration of the message decoding based on the error location polynomial, such as by obtaining the degree of the error location polynomial and comparing it to a threshold. In one example, the threshold is the maximum number of symbol errors correctable by the Reed-Solomon code embodied in the decoder. The stopping mechanism allows additional iterations when the stopping criterion (or polynomial degree) is greater than the maximum number of symbol errors correctable by the Reed-Solomon code.

20120069891, Mar 22, 2012

Sep 21, 2010

12/887330

Haotian Zhang - Longmont CO, US
Hongwei Song - Longmont CO, US
Jingfeng Liu - Longmont CO, US
Yu Liao - Longmont CO, US

H03K 5/159

375232

Various embodiments of the present invention provide systems and methods for calibrating a data processing circuit. For example, a method for calibrating a data processing circuit is discussed that includes providing a digital filter, providing a detector circuit, and providing an analog filter. Operation of the digital filter is at least in part governed by filter taps that correspond to a filter tap constraint value. Operation of the detector circuit is at least in part governed by a target parameter. Operation of the analog filter is at least in part governed by an analog parameter that is one of a plurality of analog parameters. The methods further include selecting a target parameter, and calculating the filter tap constraint value based on the target parameter. Combinations of the target parameter, the calculated filter tap constraint value, and each of the plurality of analog parameters are applied to identify the analog parameter.

20120158810, Jun 21, 2012

Dec 20, 2010

12/972942

Yu Liao - Longmont CO, US
Hongwei Song - Longmont CO, US
Lingyan Sun - Longmont CO, US

G06F 17/10

708322

Various embodiments of the present invention provide systems and methods for reducing filter sensitivities. As an example, reduced sensitivity filter circuits are discussed that include a digital filter and a filter tap adaptation circuit. The digital filter is operable to filter a received input based at least in part on a plurality of filter taps, and to provide a filtered output. The filter tap adaptation circuit is operable to receive an error value and a weighting control value, and to adaptively calculate at least one of the filter taps using the error value and the weighting control value.

20130097213, Apr 18, 2013

Oct 12, 2011

13/272209

Yu Liao - Longmont CO, US
Hongwei Song - Longmont CO, US
Jingfeng Liu - Longmont CO, US
Haotian Zhang - Longmont CO, US

G06F 17/10

708306

Various embodiments of the present invention provide apparatuses and methods for filtering a digital signal with a Nyquist constrained digital finite impulse response filter. For example, an apparatus for filtering digital data is disclosed that includes a digital finite impulse response filter having a plurality of taps. The apparatus also includes a tap weight controller connected to the digital finite impulse response filter, operable to adjust a tap weight for each of a subset of the taps such that a magnitude of a Nyquist response of the digital finite impulse response filter remains within a constraint range.

20130235484, Sep 12, 2013

Apr 12, 2012

13/445878

Yu Liao - Longmont CO, US
Haitao Xia - San Jose CA, US
Jun Xiao - Fremont CA, US

LSI Corporation - Milpitas CA

H04L 27/06
G11B 20/10

360 39, 375340, G9B 20009

Various embodiments of the present invention provide apparatuses and methods for processing data in a multi-path data processing circuit. For example, an apparatus is disclosed that includes a first filter operable to process a first digital data stream to yield a first filtered digital data stream, a second filter operable to process a second digital data stream to yield a second filtered digital data stream, wherein the first and second digital data stream are representative of a same data set and wherein the first and second digital data stream have a different phase, a combining circuit operable to combine the first filtered digital data stream and the second filtered digital data stream to yield a combined data stream, and a data detector operable to detect a data sequence in the combined data stream.