Yu Chen

6406861, Jun 18, 2002

Oct 6, 1999

09/413044

Daniel R. Henderson - Palo Alto CA
Yu Chen - Sunnyvale CA
De Chao Yu - Foster City CA

Cell Genesys, Inc. - Foster City CA

G01N 3353

435 71, 4241401, 4242331, 4241311, 4241591, 4242781, 424 931, 530351, 514885

Methods of reducing pre-existing humoral immunity to a viral immunogenic therapeutic agent such as adenovirus, using immunoapheresis are disclosed. Antibodies specific for the viral immunogenic therapeutic agent are selectively removed from the blood of an individual prior to administration of the viral immunogenic therapeutic agent by reaction extracorporeally with an immunosorbent which specifically binds the antibody. After the antibody is selectively removed from the blood, the blood is reinfused into the patient and the viral immunogenic therapeutic agent is administered. The invention also provides kits and compositions for selective removal of anti-viral antibody.

6548893, Apr 15, 2003

Jul 3, 2001

09/898567

Yu Ju Chen - San Ramon CA
Hui Wu - Milpitas CA

BigBear Networks, Inc. - Milpitas CA

H01L 2312

257704, 257693, 257710, 257728

An apparatus and method for hermetically sealing, EMI shielding integrated circuits for high-speed electronic devices using a combination of microstrip to buried stripline interface for signal transmission from the integrated circuit. The packaging provided comprises a first plurality of microstrips interconnecting the integrated circuit to a plurality of buried striplines exposed on a surface of the main substrate. A ceramic interposer placed over the main substrate âburiesâ a portion of the exposed striplines on the main substrate to thereby insulate these signal paths from a hermetically sealing, and EMI shielding metal lid placed over the integrated circuit. The metal lid and the seal ring brazed over the ceramic interposer thus provide both a hermetic seal and an electric radiation block. A reduction in dispersion due to the buried striplines is also achieved, as well as improving jitter performance.

6697260, Feb 24, 2004

Oct 29, 2001

10/040421

Yu Ju Chen - San Ramon CA
Thomas J. Sleboda - Milpitas CA
Michael Zhong Xuan Wong - Milpitas CA
Hui Wu - Milpitas CA

Big Bear Networks, Inc. - Milpitas CA

H05K 500

361752, 361753, 361736, 361735, 361785, 361803, 361796

An integrated high-speed package comprising a package housing having a housing lip and connector having a center pin abutting along a bottom surface of the housing lip. For signal registration of a first substrate to the signal lead, the substrate is âfloatedâ up to the housing lip, which provides an alignment reference to ensure that the top surface of the first substrate is aligned and in direct registration with the signal lead. In another embodiment, the center pin to substrate registration is provided at a top surface of a housing base. The housing base preferably comprises a first portion of a first height and a second portion of a second height. Accordingly, the housing base can accommodate substrates of different thickness while allowing a top surface of the first and a second substrate to be coplanar to facilitate signal registration there between.

6825068, Nov 30, 2004

Apr 17, 2001

09/836884

Kevin L. Denis - Beverly Farms MA
Yu Chen - Cambridge MA
Paul S. Drzaic - Lexington MA
Joseph M. Jacobson - Newton Centre MA
Peter T. Kazlas - Sudbury MA

E Ink Corporation - Cambridge MA

H01L 2100

438149, 438155

Transistors are formed by depositing at least one layer of semiconductor material on a substrate comprising a polyphenylene polyimide. The substrate permits the use of processing temperatures in excess of 300Â C. during the processes used to form the transistors, thus allowing the formation of high quality silicon semiconductor layers. The substrate also has a low coefficient of thermal expansion, which closely matches that of silicon, thus reducing any tendency for a silicon layer to crack or delaminate.

7030412, Apr 18, 2006

May 5, 2000

09/565413

Paul S. Drzaic - Lexington MA, US
Karl R. Amundson - Cambridge MA, US
Gregg M. Duthaler - Brookline MA, US
Peter T. Kazlas - Sudbury MA, US
Yu Chen - Cambridge MA, US

E Ink Corporation - Cambridge MA

H01L 29/04

257 59, 257 72

A thin-film transistor array comprises at least first and second transistors. Each transistor comprises a source electrode, a drain electrode a semiconductor electrode, a gate electrode, and a semiconductor layer. The semiconductor layer is continuous between the first and second transistors. The semiconductor layer is preferably unpatterned. In various display applications, the geometry of the transistors is selected to provide acceptable leakage currents. In a preferred embodiment, the transistor array is employed in an encapsulated electrophoretic display.

7116318, Oct 3, 2006

Apr 24, 2003

10/249618

Karl R. Amundson - Cambridge MA, US
Yu Chen - Allston MA, US
Kevin L. Denis - Beverly Farms MA, US
Paul S. Drzaic - Morgan Hill CA, US
Peter T. Kazlas - Sudbury MA, US
Andrew P. Ritenour - Medford MA, US

E Ink Corporation - Cambridge MA

G09G 5/00

345204, 345205, 345210, 345214

A display pixel unit provides reduced capacitative coupling between a pixel electrode and a source line. The unit includes a transistor, the pixel electrode, and the source line. The source line includes an extension that provides a source for the transistor. A patterned conductive portion is disposed adjacent to the source line.

7190008, Mar 13, 2007

Oct 27, 2004

10/904160

Karl R. Amundson - Cambridge MA, US
Andrew P. Ritenour - Medford MA, US
Gregg M. Duthaler - Needham MA, US
Paul S. Drzaic - Morgan Hill CA, US
Yu Chen - Milpitas CA, US
Peter T. Kazlas - Sudbury MA, US

E Ink Corporation - Cambridge MA

H01L 27/148
H01L 29/768

257226, 257222, 359 51

An electro-optic display comprises a substrate (), non-linear devices () disposed substantially in one plane on the substrate (), pixel electrodes () connected to the non-linear devices (), an electro-optic medium () and a common electrode () on the opposed side of the electro-optic medium () from the pixel electrodes (). The moduli of the various parts of the display are arranged so that, when the display is curved, the neutral axis or neutral plane lies substantially in the plane of the non-linear devices ().

7365394, Apr 29, 2008

Aug 17, 2004

10/919657

Kevin L Denis - Beverly Farms MA, US
Yu Chen - Cambridge MA, US
Paul S Drzaic - Morgan Hill CA, US
Joseph M Jacobson - Newton Centre MA, US
Peter T Kazlas - Sudbury MA, US

E Ink Corporation - Cambridge MA

H01L 27/01

257347, 257E29117

Transistors are formed by depositing at least one layer of semiconductor material on a substrate comprising a polyphenylene polyimide. The substrate permits the use of processing temperatures in excess of 300 C. during the processes used to form the transistors, thus allowing the formation of high quality silicon semiconductor layers. The substrate also has a low coefficient of thermal expansion, which closely matches that of silicon, thus reducing any tendency for a silicon layer to crack or delaminate.